中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

135 records (took 0.022 seconds)

    METHODS OF FORMING SELF-ALIGNED CONTACT STRUCTURES ON SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES
    21.
    发明申请
    METHODS OF FORMING SELF-ALIGNED CONTACT STRUCTURES ON SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES 有权
    在半导体器件和结构器件上形成自对准接触结构的方法

    公开(公告)号：US20160163585A1

    公开(公告)日：2016-06-09

    申请号：US14674460

    申请日：2015-03-31

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Andre Labonte

    IPC: H01L21/768 ,  H01L29/45 ,  H01L29/417 ,  H01L21/283 ,  H01L29/66

    CPC classification number: H01L21/76843 ,  H01L21/283 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66628

    Abstract: One method disclosed includes, among other things, forming a structure comprised of an island of a first insulating material positioned between the gate structures above the source/drain region and under a masking layer feature of a patterned masking layer, forming a liner layer that contacts the island of insulating material and the masking layer feature, selectively removing the masking layer feature to thereby form an initial opening that is defined by the liner layer, performing at least one isotropic etching process through the initial opening to remove the island of first insulating material and thereby define a contact opening that exposes the source/drain region, and forming a conductive contact structure in the contact opening that is conductively coupled to the source/drain region.

    Abstract translation: 所公开的一种方法包括形成由位于源/漏区之上的栅极结构之间的第一绝缘材料的岛和图案化掩模层的掩模层特征之下的一个结构，形成接触 绝缘材料岛和掩模层特征，选择性地去除掩模层特征，从而形成由衬里层限定的初始开口，通过初始开口进行至少一个各向同性蚀刻工艺以去除第一绝缘材料岛 从而限定暴露源极/漏极区域的接触开口，以及在与源极/漏极区域导电耦合的接触开口中形成导电接触结构。

    Low line resistivity and repeatable metal recess using CVD cobalt reflow
    22.
    发明授权
    Low line resistivity and repeatable metal recess using CVD cobalt reflow 有权
    低线电阻率和可重复金属凹槽使用CVD钴回流

    公开(公告)号：US09362377B1

    公开(公告)日：2016-06-07

    申请号：US14633998

    申请日：2015-02-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hoon Kim ,  Vimal Kamineni ,  Min Gyu Sung ,  Chanro Park

    IPC: H01L21/44 ,  H01L23/52 ,  H01L29/49 ,  H01L21/28 ,  H01L21/285 ,  H01L21/321 ,  H01L21/02 ,  H01L21/311

    CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/32134 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

    Abstract: Methods for forming a semiconductor gate electrode with a reflowed Co layer and the resulting device are disclosed. Embodiments include forming a trench in an ILD on a substrate; forming a high-k dielectric layer, a WF layer, and a Co layer sequentially on sidewall and bottom surfaces of the trench; reflowing a portion of the Co layer from the WF layer on the sidewall surfaces of the trench to the WF layer on the bottom surface of the trench; removing a remainder of the Co layer from the WF layer on the sidewall surfaces of the trench, above an upper surface of the reflowed Co; recessing the WF layer to the upper surface of the reflowed Co layer, forming a cavity above the reflowed Co layer; and filling the cavity with metal to form a gate electrode.

    Abstract translation: 公开了用于形成具有回流Co层的半导体栅电极的方法和所得到的器件。 实施例包括在衬底上形成ILD中的沟槽; 在沟槽的侧壁和底表面上依次形成高k电介质层，WF层和Co层; 将Co层的一部分从沟槽的侧壁表面上的WF层回流到沟槽的底表面上的WF层; 从所述沟槽的侧壁表面上的所述WF层中除去所述Co层的剩余部分，在所述回流Co的上表面上方; 将WF层凹陷到回流Co层的上表面，在回流Co层上方形成空腔; 并用金属填充空腔以形成栅电极。

    Alternative gate dielectric films for silicon germanium and germanium channel materials
    24.
    发明授权
    Alternative gate dielectric films for silicon germanium and germanium channel materials 有权
    硅锗和锗通道材料的替代栅介质膜

    公开(公告)号：US09263541B2

    公开(公告)日：2016-02-16

    申请号：US14261559

    申请日：2014-04-25

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Shariq Siddiqui ,  Bhagawan Sahu ,  Rohit Galatage ,  Hoon Kim

    IPC: H01L21/00 ,  H01L21/16 ,  H01L29/51 ,  H01L21/02

    CPC classification number: H01L29/513 ,  H01L21/28255 ,  H01L29/517

    Abstract: Embodiments of the present invention provide a high-K dielectric film for use with silicon germanium (SiGe) or germanium channel materials, and methods of fabrication. As a first step of this process, an interfacial layer (IL) is formed on the semiconductor substrate providing reduced interface trap density. However, an ultra-thin layer is used as a barrier film to avoid germanium diffusion in high-k film and oxygen diffusion from the high-k film to the interfacial layer (IL), therefore, dielectric films such as aluminum oxide (Al2O3), zirconium oxide, or lanthanum oxide (La2O3) may be used. In addition, these films can provide high thermal budget. A second dielectric layer is then deposited on the first dielectric layer. The second dielectric layer is a high-k dielectric layer, providing a reduced effective oxide thickness (EOT), resulting in improved device performance.

    Abstract translation: 本发明的实施方案提供了用于硅锗（SiGe）或锗通道材料的高K电介质膜及其制造方法。 作为该方法的第一步，在半导体衬底上形成界面层（IL），提供降低的界面陷阱密度。 然而，使用超薄层作为阻挡膜，以避免高k膜中的锗扩散和从高k膜到界面层（IL）的氧扩散，因此，诸如氧化铝（Al 2 O 3）的介电膜， ，氧化锆或氧化镧（La 2 O 3）。 此外，这些电影可以提供高热预算。 然后在第一介电层上沉积第二介电层。 第二电介质层是高k电介质层，提供有效的氧化物厚度（EOT）降低，从而提高器件性能。

    Method for reducing wettability of interconnect material at corner interface and device incorporating same
    25.
    发明授权
    Method for reducing wettability of interconnect material at corner interface and device incorporating same 有权
    用于降低角接合处的互连材料的润湿性和结合其的装置的方法

    公开(公告)号：US09209135B2

    公开(公告)日：2015-12-08

    申请号：US14227807

    申请日：2014-03-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xunyuan Zhang ,  Hoon Kim ,  Vivian W. Ryan

    IPC: H01L23/532 ,  H01L21/768

    CPC classification number: H01L23/53238 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76883 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a recess defined in a dielectric layer, the recess having an upper sidewall portion extending to an upper corner of the recess and a lower sidewall portion below the upper sidewall portion. An interconnect structure is positioned in the recess. The interconnect structure includes a continuous liner layer having upper and lower layer portions positioned laterally adjacent to the upper and lower sidewall portions, respectively. The upper layer portion includes an alloy of a first transition metal and a second transition metal and the lower layer portion includes the second transition metal but not the first transition metal. The interconnect structure also includes a fill material substantially filling the recess, wherein the second transition metal has a higher wettability for the fill material than the alloy.

    Abstract translation: 半导体器件包括限定在电介质层中的凹部，凹部具有延伸到凹部的上角部的上侧壁部分和在上侧壁部分下方的下侧壁部分。 互连结构定位在凹槽中。 互连结构包括连续的衬垫层，其具有分别位于上下侧壁部分的横向相邻的上层和下层部分。 上层部分包括第一过渡金属和第二过渡金属的合金，下层部分包括第二过渡金属，但不包括第一过渡金属。 互连结构还包括基本上填充凹部的填充材料，其中第二过渡金属对于填充材料具有比合金更高的润湿性。

    Semiconductor gate structure for threshold voltage modulation and method of making same
    28.
    发明授权
    Semiconductor gate structure for threshold voltage modulation and method of making same 有权
    用于阈值电压调制的半导体栅极结构及其制造方法

    公开(公告)号：US08932923B2

    公开(公告)日：2015-01-13

    申请号：US13770493

    申请日：2013-02-19

    Applicant: Globalfoundries, Inc.

    Inventor： Hoon Kim ,  Kisik Choi

    IPC: H01L21/8238 ,  H01L29/40 ,  H01L29/49

    CPC classification number: H01L29/401 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

    Abstract: A gate structure of a semiconductor device having a NFET and a PFET, includes a lower layer of a hafnium-based dielectric over the gates of the NFET and PFET, and an upper layer of a lanthanide dielectric. The dielectrics are annealed to mix them above the NFET resulting in a lowered work function, and corresponding threshold voltage reduction. An annealed, relatively thick titanium nitride cap over the mixed dielectric above the NFET gate also lowers the work function and threshold voltage. Above the TiN cap and the hafnium-based dielectric over the PFET gate, is another layer of titanium nitride that has not been annealed. A conducting layer of tungsten covers the structure.

    Abstract translation: 具有NFET和PFET的半导体器件的栅极结构包括在NFET和PFET的栅极上方的基于铪的电介质的下层和镧系元素电介质的上层。 将电介质退火以将其混合在NFET上方，导致降低的功函数和相应的阈值电压降低。 在NFET栅极上方的混合电介质上的退火的较厚的氮化钛盖也降低了功函数和阈值电压。 在PFET栅极上的TiN盖和铪基电介质之上，是未经退火的另一层氮化钛。 钨的导电层覆盖该结构。

    AIR-GAP SPACERS FOR FIELD-EFFECT TRANSISTORS
    30.
    发明申请
    AIR-GAP SPACERS FOR FIELD-EFFECT TRANSISTORS 审中-公开

    公开(公告)号：US20190198381A1

    公开(公告)日：2019-06-27

    申请号：US16288780

    申请日：2019-02-28

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Ruilong Xie

    IPC: H01L21/768 ,  H01L29/66

    CPC classification number: H01L21/7682 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

    Abstract: Structures for air-gap spacers in a field-effect transistor and methods for forming air-gap spacers in a field-effect transistor. A gate structure is formed on a top surface of a semiconductor body. A dielectric spacer is formed adjacent to a vertical sidewall of the gate structure. A semiconductor layer is formed on the top surface of the semiconductor body. The semiconductor layer is arranged relative to the vertical sidewall of the gate structure such that a first section of the first dielectric spacer is located in a space between the semiconductor layer and the vertical sidewall of the gate structure. A second section of the dielectric spacer that is located above a top surface of the semiconductor layer is removed. An air-gap spacer is formed in a space from which the second section of the dielectric spacer is removed.

Patent Agency Ranking