公开(公告)号：US20140273429A1

公开(公告)日：2014-09-18

申请号：US13797117

申请日：2013-03-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andy C. Wei ,  Dae Geun Yang

IPC: H01L29/40

CPC classification number: H01L29/401 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545

Abstract: In one example, the method disclosed herein includes forming a shared sacrificial gate structure above at least one first fin for a first type of FinFET device and at least one second fin for a second type of FinFET device, wherein the second type is opposite to the first type, and forming a first sidewall spacer around an entire perimeter of the sacrificial gate structure in a single process operation.

Abstract translation: 在一个示例中，本文公开的方法包括在用于第一类型的FinFET器件的至少一个第一鳍上方形成共用牺牲栅极结构，以及在第二类型的FinFET器件中形成至少一个第二鳍，其中第二类型与 并且在单个工艺操作中在牺牲栅极结构的整个周边周围形成第一侧壁间隔物。

公开(公告)号：US08753940B1

公开(公告)日：2014-06-17

申请号：US13834410

申请日：2013-03-15

Applicant: Globalfoundries Inc.

Inventor： Andy C. Wei ,  Dae Geun Yang

IPC: H01L21/336

CPC classification number: H01L21/845 ,  H01L21/823431

Abstract: One method includes forming a plurality of trenches in a semiconducting substrate to define a plurality of fins, forming a layer of overfill material that overfills the trenches, wherein an upper surface of the overfill material is positioned above an upper surface of the fins, forming a masking layer above the layer of overfill material, wherein the masking layer has an opening that is positioned above a subset of the plurality of fins that is desired to be removed and wherein the subset of fins is comprised of at least one but less than all of the fins, performing an etching process through the masking layer to remove at least a portion of the layer of overfill material and expose the upper surface of the subset of fins, and performing a second etching process on the exposed surface of the subset of fins to remove the subset of fins.

Abstract translation: 一种方法包括在半导体衬底中形成多个沟槽以限定多个翅片，形成覆盖沟槽的填充材料层，其中，所述填充材料的上表面位于所述翅片的上表面上方，形成 掩蔽层，其中所述掩蔽层具有位于所述多个翅片的子集上方的开口，所述多个翅片的子集需要被去除，并且其中所述翅片的子集包括至少一个但不是全部的 翅片，通过掩模层进行蚀刻工艺，以去除覆盖层材料层的至少一部分，并暴露散热片子组的上表面，并对翅片子组的暴露表面进行第二蚀刻工艺，以 去除鳍片的子集。

公开(公告)号：US09660075B2

公开(公告)日：2017-05-23

申请号：US15051734

申请日：2016-02-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Shao Ming Koh ,  Guillaume Bouche ,  Jeremy A. Wahl ,  Andy C. Wei

IPC: H01L21/84 ,  H01L29/78 ,  H01L27/092 ,  H01L21/311 ,  H01L29/45 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/167 ,  H01L29/161 ,  H01L21/02 ,  H01L29/08 ,  H01L29/24 ,  H01L29/66 ,  H01L29/417 ,  H01L27/12

CPC classification number: H01L29/7839 ,  H01L21/02532 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/24 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/7848

Abstract: Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures having source/drain regions in PFET areas and in NFET areas. The method includes selectively forming a contact resistance modulation material on the source/drain regions in the PFET areas. Further, the method includes depositing a band-edge workfunction metal overlying the source/drain regions in the PFET areas and in the NFET areas.

公开(公告)号：US09431512B2

公开(公告)日：2016-08-30

申请号：US14308257

申请日：2014-06-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shao-Ming Koh ,  Guillaume Bouche ,  Jing Wan ,  Andy C. Wei

IPC: H01L21/336 ,  H01L29/66 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/775 ,  H01L29/06

CPC classification number: H01L29/66439 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/66492 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/775

Abstract: A method of forming a nanowire device includes forming semiconductor material layers above a semiconductor substrate, forming a gate structure above the semiconductor material layers, forming a first sidewall spacer adjacent to the gate structure and forming a second sidewall spacer adjacent to the first sidewall spacer. The method further includes patterning the semiconductor material layers such that each layer has first and second exposed end surfaces. The gate structure, the first sidewall spacer, and the second sidewall spacer are used in combination as an etch mask during the patterning process. The method further includes removing the first and second sidewall spacers, thereby exposing at least a portion of the patterned semiconductor material layers. The method further includes forming doped extension regions in at least the exposed portions of the patterned semiconductor material layers after removing the first and second sidewall spacers.

Abstract translation: 形成纳米线器件的方法包括在半导体衬底之上形成半导体材料层，在半导体材料层之上形成栅极结构，形成与栅极结构相邻的第一侧壁间隔物，并形成邻近第一侧壁间隔物的第二侧壁间隔物。 该方法还包括使半导体材料层图案化，使得每个层具有第一和第二暴露的端表面。 栅极结构，第一侧壁间隔件和第二侧壁间隔件在图案化工艺期间被组合用作蚀刻掩模。 该方法还包括去除第一和第二侧壁间隔物，从而暴露图案化的半导体材料层的至少一部分。 该方法还包括在除去第一和第二侧壁间隔物之后，在至少图案化的半导体材料层的暴露部分中形成掺杂的延伸区域。

公开(公告)号：US09412655B1

公开(公告)日：2016-08-09

申请号：US14608377

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jason E. Stephens ,  Vikrant Chauhan ,  Andy C. Wei

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/308 ,  H01L21/033

CPC classification number: H01L21/3081 ,  H01L21/0334 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897

Abstract: A method includes forming a plurality of sacrificial lines embedded in a first dielectric layer. A line merge opening and a line cut opening are formed in a hard mask layer formed above the first dielectric layer. Portions of the first dielectric layer exposed by the line merge opening are removed to define a line merge recess. A portion of a selected sacrificial line exposed by the line cut opening is removed to define a line cut recess between first and second segments of the selected sacrificial line. A second dielectric layer is formed in the line cut recess. The hard mask is removed. The plurality of sacrificial lines is replaced with a conductive material to define at least one line having third and fourth segments in locations previously occupied by the first and second segments and to define a line-merging conductive structure in the line merge recess.

Abstract translation: 一种方法包括形成埋在第一介电层中的多条牺牲线。 在形成在第一电介质层上方的硬掩模层中形成线合并开口和线切口。 去除由线合并开口露出的第一电介质层的部分以限定线合并凹槽。 通过线切割开口暴露的所选牺牲线的一部分被去除以在所选牺牲线的第一和第二段之间限定线切割凹槽。 第二介质层形成在线切割凹部中。 硬面膜被去除。 多个牺牲线被导电材料代替，以限定在先前由第一和第二段占据的位置中限定具有第三和第四段的至少一个线，并且在线合并凹槽中限定线路合并导电结构。

公开(公告)号：US20160225666A1

公开(公告)日：2016-08-04

申请号：US14608377

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jason E. Stephens ,  Vikrant Chauhan ,  Andy C. Wei

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/3081 ,  H01L21/0334 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897

Abstract: A method includes forming a plurality of sacrificial lines embedded in a first dielectric layer. A line merge opening and a line cut opening are formed in a hard mask layer formed above the first dielectric layer. Portions of the first dielectric layer exposed by the line merge opening are removed to define a line merge recess. A portion of a selected sacrificial line exposed by the line cut opening is removed to define a line cut recess between first and second segments of the selected sacrificial line. A second dielectric layer is formed in the line cut recess. The hard mask is removed. The plurality of sacrificial lines is replaced with a conductive material to define at least one line having third and fourth segments in locations previously occupied by the first and second segments and to define a line-merging conductive structure in the line merge recess.

Abstract translation: 一种方法包括形成埋在第一介电层中的多条牺牲线。 在形成在第一电介质层上方的硬掩模层中形成线合并开口和线切口。 去除由线合并开口露出的第一电介质层的部分以限定线合并凹槽。 通过线切割开口暴露的所选牺牲线的一部分被去除以在所选牺牲线的第一和第二段之间限定线切割凹槽。 第二介质层形成在线切割凹部中。 硬面膜被去除。 多个牺牲线被导电材料代替，以限定在先前由第一和第二段占据的位置中限定具有第三和第四段的至少一个线，并且在线合并凹槽中限定线路合并导电结构。

公开(公告)号：US08969932B2

公开(公告)日：2015-03-03

申请号：US13711779

申请日：2012-12-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Akshey Sehgal ,  Seung Y. Kim ,  Teck Jung Tang ,  Francis M. Tambwe

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903

Abstract: One method disclosed herein includes, prior to forming an isolation region in a semiconducting substrate for the device, forming a doped well region and a doped punch-stop region in the substrate, introducing a dopant material that is adapted to retard diffusion of boron or phosphorous into the substrate to form a dopant-containing layer proximate an upper surface of the substrate, performing an epitaxial deposition process to form an undoped semiconducting material above the dopant-containing layer, forming a plurality of spaced-apart trenches that extend at least partially into the substrate, wherein the trenches define a fin for the device comprised of at least the undoped semiconducting material, forming at least a local isolation insulating material in the trenches, and forming a gate structure around at least the undoped semiconducting material, wherein a bottom of a gate electrode is positioned approximately level with or below a bottom of the undoped semiconducting material.

Abstract translation: 本文公开的一种方法包括：在用于器件的半导体衬底中形成隔离区之前，在衬底中形成掺杂阱区和掺杂的穿通停止区，引入适于延迟硼或磷扩散的掺杂​​材料 进入衬底以在衬底的上表面附近形成含掺杂剂的层，执行外延沉积工艺以在掺杂剂层之上形成未掺杂的半导体材料，形成多个间隔开的沟槽，其至少部分延伸到 衬底，其中所述沟槽限定用于由至少所述未掺杂的半导体材料构成的器件的鳍，在所述沟槽中形成至少一个局部隔离绝缘材料，以及形成至少所述未掺杂的半导体材料周围的栅极结构，其中， 栅极位于与未掺杂的半导体材料的底部大致平齐的位置。

公开(公告)号：US20140273369A1

公开(公告)日：2014-09-18

申请号：US13798429

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andy C. Wei ,  Shao Ming Koh

IPC: H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/66606 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545

Abstract: In one example, the method disclosed herein includes forming at least one fin for a FinFET device in a semiconducting substrate, performing at least one process operation to form a region in the at least one fin that contains a metal diffusion inhibiting material, depositing a layer of metal on the region in the at least one fin and forming a metal silicide region on the at least one fin.

Abstract translation: 在一个示例中，本文公开的方法包括在半导体衬底中形成用于FinFET器件的至少一个鳍，执行至少一个工艺操作以在至少一个鳍中形成包含金属扩散抑制材料的区域， 的至少一个翅片上的区域上的金属，并在所述至少一个翅片上形成金属硅化物区域。

公开(公告)号：US20140159126A1

公开(公告)日：2014-06-12

申请号：US13711779

申请日：2012-12-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andy C. Wei ,  Akshey Sehgal ,  Seung Y. Kim ,  Teck Jung Tang ,  Francis M. Tambwe

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903

Abstract: One method disclosed herein includes, prior to forming an isolation region in a semiconducting substrate for the device, forming a doped well region and a doped punch-stop region in the substrate, introducing a dopant material that is adapted to retard diffusion of boron or phosphorous into the substrate to form a dopant-containing layer proximate an upper surface of the substrate, performing an epitaxial deposition process to form an undoped semiconducting material above the dopant-containing layer, forming a plurality of spaced-apart trenches that extend at least partially into the substrate, wherein the trenches define a fin for the device comprised of at least the undoped semiconducting material, forming at least a local isolation insulating material in the trenches, and forming a gate structure around at least the undoped semiconducting material, wherein a bottom of a gate electrode is positioned approximately level with or below a bottom of the undoped semiconducting material.

Abstract translation: 本文公开的一种方法包括：在用于器件的半导体衬底中形成隔离区之前，在衬底中形成掺杂阱区和掺杂的穿通停止区，引入适于延迟硼或磷扩散的掺杂​​材料 进入衬底以在衬底的上表面附近形成含掺杂剂的层，执行外延沉积工艺以在掺杂剂层之上形成未掺杂的半导体材料，形成多个间隔开的沟槽，其至少部分延伸到 衬底，其中所述沟槽限定用于由至少所述未掺杂的半导体材料构成的器件的鳍，在所述沟槽中形成至少一个局部隔离绝缘材料，以及形成至少所述未掺杂的半导体材料周围的栅极结构，其中， 栅极位于与未掺杂的半导体材料的底部大致平齐的位置。

公开(公告)号：US20140131831A1

公开(公告)日：2014-05-15

申请号：US13674311

申请日：2012-11-12

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Andy C. Wei ,  Konstantin Korablev ,  Francis Tambwe

IPC: H01L27/08 ,  H01L21/77

CPC classification number: H01L21/77 ,  H01L21/823431 ,  H01L27/0629 ,  H01L27/0886

Abstract: A method is provided for forming an integrated circuit having a diode. The method includes forming at least one fin in a shallow trench isolation (STI) oxide layer disposed above a substrate layer. The at least one fin extends from a bottom end adjacent the substrate layer to a top end. The method further includes adding a cathode implant in a first region of the at least one fin and the substrate layer and adding an anode implant in a second region of the at least one fin and the substrate layer such that a junction is formed in the substrate layer below the at least one fin. The method also includes etching away a portion of the STI oxide layer to expose the top end of the at least one fin.

Abstract translation: 提供一种用于形成具有二极管的集成电路的方法。 该方法包括在设置在基底层上方的浅沟槽隔离（STI）氧化物层中形成至少一个翅片。 至少一个翅片从邻近基底层的底端延伸到顶端。 该方法还包括在至少一个鳍片和衬底层的第一区域中添加阴极植入物，并且在至少一个翅片和衬底层的第二区域中添加阳极植入物，使得在衬底中形成结 在至少一个翅片下方的层。 该方法还包括蚀刻掉STI氧化物层的一部分以露出至少一个翅片的顶端。