公开(公告)号：US10236291B2

公开(公告)日：2019-03-19

申请号：US15801023

申请日：2017-11-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie ,  Kwan-Yong Lim

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/32 ,  H01L21/311 ,  H01L21/302 ,  H01L21/461 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/78

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess level in a field region adjacent to a fin array region comprising a plurality of fins in a finFET device. The first oxide process comprises depositing an oxide layer over the field region and the fin array region and performing an oxide recess process to bring the oxide layer to the first oxide recess level in the field region. A second oxide process is performed for controlling a second oxide recess level in the fin array region. The second oxide process comprises isolating the fin array region, depositing oxide material, and performing an oxide recess process to bring the oxide level in the fin array region to the second oxide recess level. The first oxide recess level is within a predetermined height differential of the second oxide recess level.

公开(公告)号：US10141446B2

公开(公告)日：2018-11-27

申请号：US15793545

申请日：2017-10-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki Niimi ,  Kwan-Yong Lim ,  Steven John Bentley ,  Daniel Chanemougame

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/306 ,  H01L21/265 ,  H01L27/24 ,  H01L29/792 ,  H01L29/78

Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.

公开(公告)号：US20180033789A1

公开(公告)日：2018-02-01

申请号：US15224139

申请日：2016-07-29

Applicant: GLOBALFOUNDRIES INC. ,  International Business Machines Corporation

Inventor： Steven Bentley ,  Kwan-Yong Lim ,  Tenko Yamashita ,  Gauri Karve ,  Sanjay Mehta

IPC: H01L27/092 ,  H01L21/306 ,  H01L21/762 ,  H01L21/266 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265 ,  H01L21/8238 ,  H01L29/167

CPC classification number: H01L27/0924 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/66803

Abstract: We disclose semiconductor devices, comprising a semiconductor substrate comprising a substrate material; and a plurality of fins disposed on the substrate, each fin comprising a lower region comprising the substrate material, a dopant region disposed above the lower region and comprising at least one dopant, and a channel region disposed above the dopant region and comprising a semiconductor material, wherein the channel region comprises less than 1×1018 dopant molecules/cm3, as well as methods, apparatus, and systems for fabricating such semiconductor devices.

公开(公告)号：US09865704B2

公开(公告)日：2018-01-09

申请号：US15168690

申请日：2016-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Kwan-Yong Lim ,  Min Gyu Sung ,  Ryan Ryoung-Han Kim

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: One illustrative integrated circuit product disclosed herein includes, among other things, a plurality of FinFET devices, each of which comprises a gate structure comprising a high-k gate insulation material and at least one layer of metal, a single diffusion break (SDB) isolation structure positioned in a first trench defined in a semiconductor substrate between first and second active regions, the SDB isolation structure comprising the high-k insulating material and the at least one layer of metal, and a double diffusion break (DDB) isolation structure positioned in a second trench defined in a semiconductor substrate between third and fourth active regions, the DDB isolation structure comprising a first insulating material that substantially fills the second trench.

公开(公告)号：US09859125B2

公开(公告)日：2018-01-02

申请号：US15072626

申请日：2016-03-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Chanro Park ,  Hoon Kim ,  Kwan-Yong Lim

IPC: H01L21/311 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/11 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L21/3065 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/11 ,  H01L28/00 ,  H01L29/0642 ,  H01L29/0657 ,  H01L29/161

Abstract: Methodologies and a device for SRAM patterning are provided. Embodiments include forming a spacer layer over a fin channel, the fin channel being formed in four different device regions; forming a bottom mandrel over the spacer layer; forming a top mandrel directly over the bottom mandrel, wherein the top and bottom mandrels including different materials; forming a buffer oxide layer over the top mandrel; forming an anti-reflective coating (ARC) over the first OPL; forming a photoresist (PR) over the ARC and patterning the PR; and etching the first OPL, ARC, buffer oxide, and top mandrel with the pattern of the PR, wherein a pitch of the PR as patterned is different in each of the four device regions.

公开(公告)号：US09799751B1

公开(公告)日：2017-10-24

申请号：US15132383

申请日：2016-04-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Steven J. Bentley ,  Kwan-Yong Lim

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L21/321 ,  H01L21/265 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H01L29/66666 ,  H01L21/02164 ,  H01L21/26513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823885 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

Abstract: One illustrative method disclosed herein includes forming a multi-layered sidewall spacer (MLSS) around a vertically oriented channel semiconductor structure, wherein the MLSS comprises a non-sacrificial innermost first spacer (a high-k insulating material), a sacrificial outermost spacer and at least one non-sacrificial second spacer (a metal-containing material) positioned between the innermost spacer and the outermost spacer, removing at least a portion of the sacrificial outermost spacer from the MLSS while leaving the at least one non-sacrificial second spacer and the non-sacrificial innermost first spacer in position and forming a final conductive gate electrode in place of the removed sacrificial outermost spacer.

公开(公告)号：US09530863B1

公开(公告)日：2016-12-27

申请号：US15097574

申请日：2016-04-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Carl Radens ,  Steven J. Bentley ,  Brian A. Cohen ,  Kwan-Yong Lim

IPC: H01L21/306 ,  H01L29/66

CPC classification number: H01L29/66545 ,  H01L29/0847 ,  H01L29/66666 ,  H01L29/7827

Abstract: One illustrative method disclosed herein includes, among other things, forming a vertically oriented channel semiconductor structure, forming a layer of a bottom spacer material around the vertically oriented channel semiconductor structure and forming a sacrificial material layer above the layer of a bottom spacer material. In this example, the method further includes forming a sidewall spacer adjacent the vertically oriented channel semiconductor structure and above an upper surface of the sacrificial material layer, removing the sacrificial material layer so as to define a replacement gate cavity between a bottom surface of the sidewall spacer and the layer of a bottom spacer material, and forming a replacement gate structure in the replacement gate cavity.

Abstract translation: 本文中公开的一种说明性方法包括形成垂直取向的沟道半导体结构，在垂直取向的沟道半导体结构周围形成底部间隔物材料的层，并在底部间隔物材料的层的上方形成牺牲材料层。 在该示例中，该方法还包括形成邻近垂直取向的沟道半导体结构并且在牺牲材料层的上表面上方的侧壁间隔物，去除牺牲材料层，以便在侧壁的底表面之间限定替换栅腔 间隔物和底部间隔物材料的层，并且在替换浇口腔中形成替代浇口结构。

公开(公告)号：US09412616B1

公开(公告)日：2016-08-09

申请号：US14942448

申请日：2015-11-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Kwan-Yong Lim ,  Min Gyu Sung ,  Ryan Ryoung-Han Kim

IPC: H01L21/00 ,  H01L21/3105 ,  H01L21/027 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/283 ,  H01L21/762

CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: One illustrative method disclosed herein includes, among other things, forming a multi-layer patterned masking layer comprised of first and second layers of material and first and second openings that extend through both of the first and second layers of material, wherein the first opening is positioned above a first area of the substrate where the DDB isolation structure will be formed and the second opening is positioned above a second area of the substrate where the SDB isolation structure will be formed. The method also includes performing a first process operation through the first opening to form the DDB isolation structure, performing a second process operation to remove the second layer of material and to expose the first opening in the first layer of material, and performing a third process operation through the second opening to form the SDB isolation structure.

Abstract translation: 本文公开的一种说明性方法包括形成由第一和第二层材料构成的多层图案化掩模层，以及延伸穿过第一和第二材料层的第一和第二开口，其中第一开口是 位于基板的将形成DDB隔离结构的第一区域之上，并且第二开口位于衬底的将形成SDB隔离结构的第二区域之上。 该方法还包括通过第一开口执行第一处理操作以形成DDB隔离结构，执行第二处理操作以去除第二层材料并露出第一层材料中的第一开口，以及执行第三工艺 通过第二次开启操作形成SDB隔离结构。

公开(公告)号：US20150340468A1

公开(公告)日：2015-11-26

申请号：US14283721

申请日：2014-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong Lim ,  Min Gyu Sung ,  Jody A. Fronheiser ,  Christopher M. Prindle

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A method includes forming at least one fin in a semiconductor substrate. A sacrificial gate structure is formed around a first portion of the at least one fin. Sidewall spacers are formed adjacent the sacrificial gate structure. The sacrificial gate structure and spacers expose a second portion of the at least one fin. An epitaxial material is formed on the exposed second portion. At least one process operation is performed to remove the sacrificial gate structure and thereby define a gate cavity between the spacers that exposes the first portion of the at least one fin. The first portion of the at least one fin is recessed to a first height less than a second height of the second portion of the at least one fin. A replacement gate structure is formed within the gate cavity above the recessed first portion of the at least one fin.

Abstract translation: 一种方法包括在半导体衬底中形成至少一个翅片。 在所述至少一个翅片的第一部分周围形成牺牲栅极结构。 侧壁间隔件形成在牺牲栅极结构附近。 所述牺牲栅极结构和间隔物暴露所述至少一个翅片的第二部分。 在暴露的第二部分上形成外延材料。 执行至少一个处理操作以去除牺牲栅极结构，从而在间隔件之间限定暴露至少一个鳍片的第一部分的栅极腔。 所述至少一个翅片的第一部分凹陷到小于所述至少一个翅片的第二部分的第二高度的第一高度。 在所述至少一个翅片的凹入的第一部分上方的栅极空腔内形成替换栅极结构。

公开(公告)号：US20200020631A1

公开(公告)日：2020-01-16

申请号：US16578844

申请日：2019-09-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chun Yu Wong ,  Kwan-Yong Lim ,  Seong Yeol Mun ,  Jagar Singh ,  Hui Zang

IPC: H01L23/525 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

Abstract: One illustrative integrated circuit product disclosed herein includes a vertically oriented semiconductor (VOS) structure positioned above a semiconductor substrate, a conductive silicide vertically oriented e-fuse positioned along at least a portion of a vertical height of the VOS structure wherein the conductive silicide vertically oriented e-fuse comprises a metal silicide material that extends through at least a portion of an entire lateral width of the VOS structure, and a conductive metal silicide region in the semiconductor substrate that is conductively coupled to the conductive silicide vertically oriented e-fuse.