公开(公告)号：US20230369256A1

公开(公告)日：2023-11-16

申请号：US17742767

申请日：2022-05-12

Applicant: Infineon Technologies AG

Inventor： Kushal Kshirsagar ,  Eung San Cho ,  Danny Clavette ,  Wenkang Huang ,  Angela Kessler

IPC: H01L23/66 ,  H01L23/367 ,  H01L23/13 ,  H05K1/11 ,  H05K3/30 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L23/66 ,  H01L23/3675 ,  H01L23/13 ,  H05K1/111 ,  H05K3/301 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49872 ,  H05K2201/10431 ,  H05K2201/1003

Abstract: A semiconductor assembly includes a carrier including a dielectric substrate and a plurality of contact pads disposed on an upper surface of the carrier, first and second surface mount packages mounted on the carrier, first and second discrete inductors respectively mounted over the first and second surface mount packages, wherein the first and second surface mount packages each comprise lower surface terminals that face and electrically connect with the contact pads from the carrier, wherein the first and second surface mount packages each comprise an upper side that faces away from the carrier, and wherein the first and second discrete inductors are respectively thermally coupled to the upper sides of the first and second surface mount packages.

公开(公告)号：US20220262716A1

公开(公告)日：2022-08-18

申请号：US17176678

申请日：2021-02-16

Applicant: Infineon Technologies AG

Inventor： Angela Kessler ,  Robert Carroll ,  Robert Fehler

IPC: H01L23/498 ,  H01L25/07 ,  H01L23/00 ,  H01L21/48

Abstract: A semiconductor assembly includes an interposer that includes an insulating substrate, a plurality of upper contact pads on an upper surface of the substrate, and a plurality of lower contact pads on a lower surface of the substrate, a semiconductor package that includes a semiconductor die embedded within a package body and a plurality of package terminals exposed from the package body, a first passive electrical element that includes first and second terminals, a first electrical connection between the first terminal of the first passive electrical element and a first one of the lower contact pads via the interposer, a second electrical connection between the second terminal of the first passive electrical element and a first one of the package terminals, and a third electrical connection between a second one of the package terminals and a second one of the lower contact pads via the interposer.

公开(公告)号：US11056458B2

公开(公告)日：2021-07-06

申请号：US16690948

申请日：2019-11-21

Applicant: Infineon Technologies AG

Inventor： Angela Kessler ,  Andreas Grassmann

IPC: H01L21/56 ,  H01L23/00

Abstract: A package and method of making a package is disclosed. In one example, the package includes an electronic chip having at least one pad, an encapsulant at least partially encapsulating the electronic chip, and an electrically conductive contact element extending from the at least one pad and through the encapsulant so as to be exposed with respect to the encapsulant. The electrically conductive contact element comprises a first contact structure made of a first electrically conductive material on the at least one pad and comprises a second contact structure made of a second electrically conductive material and being exposed with respect to the encapsulant. At least one of the at least one pad has at least a surface portion which comprises or is made of the first electrically conductive material.

公开(公告)号：US10242969B2

公开(公告)日：2019-03-26

申请号：US14077696

申请日：2013-11-12

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Juergen Hoegerl ,  Angela Kessler ,  Magdalena Hoier

IPC: H01L25/07 ,  H01L23/31 ,  H01L23/522 ,  H01L25/00 ,  H01L21/56 ,  H01L23/373 ,  H01L23/433 ,  H01L23/538 ,  H01L23/498

Abstract: A semiconductor package includes a first semiconductor module including a plurality of semiconductor transistor chips and a first encapsulation layer disposed above the semiconductor transistor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of semiconductor driver channels and a second encapsulation layer disposed above the semiconductor driver channels. The semiconductor driver channels are configured to drive the semiconductor transistor chips.

公开(公告)号：US20150097282A1

公开(公告)日：2015-04-09

申请号：US14569958

申请日：2014-12-15

Applicant: Infineon Technologies AG

Inventor： Michael Bauer ,  Alfred Haimerl ,  Angela Kessler ,  Wolfgang Schober

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L21/56 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/492 ,  H01L23/49562 ,  H01L23/49805 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.

Abstract translation: 提供芯片封装，芯片封装包括：芯片载体; 芯片布置在芯片载体顶侧并电连接到芯片载体顶侧; 设置在芯片上并且至少部分地围绕芯片的电绝缘材料; 形成在所述电绝缘材料上并与所述芯片电连接的一个或多个导电接触区域; 设置在芯片载体底侧上的另外的电绝缘材料; 其中芯片载体底侧上的导电接触区域从另外的电绝缘材料释放。

公开(公告)号：US20140327458A1

公开(公告)日：2014-11-06

申请号：US13886285

申请日：2013-05-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Martin GRUBER ,  Angela Kessler

IPC: G01R27/14 ,  G01R3/00

CPC classification number: G01R27/14 ,  G01R1/203 ,  G01R3/00 ,  G01R13/347 ,  G01R15/181 ,  G01R31/2648 ,  G01R31/2884 ,  H05K1/0268 ,  H05K1/167 ,  H05K3/06 ,  H05K2201/09736 ,  H05K2201/10166 ,  H05K2203/092 ,  H05K2203/171

Abstract: A method of manufacturing an electronic circuit with an integrally formed capability of providing information indicative of a value of a current flowing in the electronic circuit, wherein the method comprises forming an electrically conductive wiring structure on a substrate, configuring a first section of the wiring structure for contributing to a predefined use function of the electronic circuit, and configuring a second section of the wiring structure for providing information indicative of the value of the current flowing in the electronic circuit upon applying a stimulus signal to the second section, wherein at least a part of the configuring of the first section and the configuring of the second section is performed simultaneously.

Abstract translation: 一种制造电子电路的方法，所述电子电路具有提供表示在所述电子电路中流动的电流的值的信息的整合能力，其中所述方法包括在基板上形成导电布线结构，构成所述布线结构的第一部分 用于对所述电子电路的预定义使用功能作出贡献，以及配置所述布线结构的第二部分，用于在向所述第二部分施加刺激信号时提供指示在所述电子电路中流动的电流的值的信息，其中至少一个 同时执行部分第一部分的配置和第二部分的配置。

公开(公告)号：US20130105992A1

公开(公告)日：2013-05-02

申请号：US13721957

申请日：2012-12-20

Applicant: Infineon Technologies AG

Inventor： Michael Bauer ,  Thomas Engling ,  Alfred Halmerl ,  Angela Kessler ,  Joachim Mahler ,  Wolfgang Schober

IPC: H01L23/538

CPC classification number: H01L23/538 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L25/0657 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

Abstract: A semiconductor component including a stack of semiconductor chips, the semiconductor chips being fixed cohesively one on top of another, is disclosed. The contact areas of the semiconductor chips are led as far as the edges of the semiconductor chips and conductor portions extend at least from an upper edge to a lower edge of the edge sides of the semiconductor chips in order to electrically connect the contact area of the stacked semiconductor chips to one another.

Abstract translation: 公开了一种包括半导体芯片的堆叠的半导体部件，半导体芯片一体地固定在另一个之上。 半导体芯片的接触区域被引导直到半导体芯片和导体部分的边缘至少从半导体芯片的边缘侧的上边缘延伸到下边缘，以便电连接半导体芯片的接触区域 堆叠的半导体芯片彼此。

公开(公告)号：US20240339371A1

公开(公告)日：2024-10-10

申请号：US18746297

申请日：2024-06-18

Applicant: Infineon Technologies AG

Inventor： Petteri Palm ,  Angela Kessler

IPC: H01L23/31 ,  H01L21/56 ,  H01L25/07

CPC classification number: H01L23/3142 ,  H01L21/561 ,  H01L21/568 ,  H01L25/072

Abstract: A method includes placing a first die comprising a frontside, a backside, a frontside metallization on the frontside and a backside metallization on the backside into at least one recess of a laminated carrier onto a removable carrier, surface-treating the metallization facing away from the removable carrier by forming an adhesion promoter material onto the metallization facing away from the removable carrier and/or by roughening the surface of the metallization facing away from the removable carrier, partially encapsulating the first die such that a first encapsulating material at least partially covers the metallization facing away from the removable carrier; and removing the removable carrier to expose at least a portion of the metallization facing the removable carrier.

公开(公告)号：US12027436B2

公开(公告)日：2024-07-02

申请号：US17575038

申请日：2022-01-13

Applicant: Infineon Technologies AG

Inventor： Angela Kessler ,  Kok Yau Chua ,  Josef Hoeglauer ,  Chiah Chin Lim ,  Mei Qi Tay

IPC: H01L29/06 ,  H01L21/52 ,  H01L23/31 ,  H01L23/495 ,  H01L23/538 ,  H01L31/072 ,  H01L31/109

CPC classification number: H01L23/3157 ,  H01L21/52 ,  H01L23/49541 ,  H01L23/5384

Abstract: A package and method of manufacturing is disclosed. In one example, the package which comprises a carrier with at least one component mounted on the carrier. A clip is arranged above the carrier and having a through hole. At least part of at least one of the at least one component and/or at least part of an electrically conductive connection element electrically connecting the at least one component is at least partially positioned inside the through hole.

公开(公告)号：US20240079310A1

公开(公告)日：2024-03-07

申请号：US18389506

申请日：2023-11-14

Applicant: Infineon Technologies AG

Inventor： Angela Kessler ,  Robert Carroll ,  Robert Fehler

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/07

CPC classification number: H01L23/49844 ,  H01L21/4853 ,  H01L24/16 ,  H01L25/072 ,  H01L2224/16227 ,  H01L2924/19104

Abstract: A method includes providing an interposer that includes an electrically insulating substrate, upper contact pads disposed on an upper surface, and lower contact pads disposed on a lower surface, providing a semiconductor package that includes a semiconductor die embedded within a package body and a plurality of package terminals exposed from the package body, providing a first passive electrical element that comprises first and second terminals, forming a first electrical connection between the first terminal of the first passive electrical element and a first one of the lower contact pads via the interposer, forming a second electrical connection between the second terminal of the first passive electrical element and a first one of the package terminals, and forming a third electrical connection between a second one of the package terminals and a second one of the lower contact pads via the interposer.