中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

37 records (took 0.021 seconds)

    Semiconductor devices including parallel electrically conductive layers
    1.
    发明授权
    Semiconductor devices including parallel electrically conductive layers 有权

    公开(公告)号：US12237246B2

    公开(公告)日：2025-02-25

    申请号：US17196652

    申请日：2021-03-09

    Applicant: Infineon Technologies AG

    Inventor： Petteri Palm ,  Robert Fehler ,  Josef Hoeglauer ,  Angela Kessler

    IPC: H01L23/485 ,  H01L23/00 ,  H01L23/31

    Abstract: A semiconductor device is disclosed. In one example, the semiconductor device includes a semiconductor chip including a first chip contact pad on a first chip main surface. The semiconductor device further includes a first electrically conductive layer arranged over the first chip main surface and electrically coupled to the first chip contact pad, wherein the first electrically conductive layer extends in a direction parallel to the first chip main surface. An electrical through connection is electrically coupled to the first electrically conductive layer and to a second electrically conductive layer, wherein the electrical through connection extends in a direction perpendicular to the first chip main surface, and wherein, in a top view of the first chip main surface, the electrical through connection and the semiconductor chip are non-overlapping.

    Die package and method of manufacturing a die package
    2.
    发明授权
    Die package and method of manufacturing a die package 有权

    公开(公告)号：US12033909B2

    公开(公告)日：2024-07-09

    申请号：US16909575

    申请日：2020-06-23

    Applicant: Infineon Technologies AG

    Inventor： Petteri Palm ,  Angela Kessler

    IPC: H01L23/31 ,  H01L21/56 ,  H01L25/07

    CPC classification number: H01L23/3142 ,  H01L21/561 ,  H01L21/568 ,  H01L25/072

    Abstract: A die package is provided. The die package may include a laminated carrier including at least one recess, a first die having a frontside, a backside, a frontside metallization on the frontside and a backside metallization on the backside, wherein the first die is arranged in the at least one recess, a first encapsulating material partially encapsulating the first die, by covering at least the frontside metallization or the backside metallization, and an adhesion promoter material between the metallization covered by the first encapsulation material and the first encapsulation material and in direct physical contact with the first encapsulation material and the metallization covered by the first encapsulation material.

    Semiconductor package and passive element with interposer
    8.
    发明授权
    Semiconductor package and passive element with interposer 有权

    公开(公告)号：US12131988B2

    公开(公告)日：2024-10-29

    申请号：US18389506

    申请日：2023-11-14

    Applicant: Infineon Technologies AG

    Inventor： Angela Kessler ,  Robert Carroll ,  Robert Fehler

    IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L25/07

    CPC classification number: H01L23/49844 ,  H01L21/4853 ,  H01L24/16 ,  H01L25/072 ,  H01L2224/16227 ,  H01L2924/19104

    Abstract: A method includes providing an interposer that includes an electrically insulating substrate, upper contact pads disposed on an upper surface, and lower contact pads disposed on a lower surface, providing a semiconductor package that includes a semiconductor die embedded within a package body and a plurality of package terminals exposed from the package body, providing a first passive electrical element that comprises first and second terminals, forming a first electrical connection between the first terminal of the first passive electrical element and a first one of the lower contact pads via the interposer, forming a second electrical connection between the second terminal of the first passive electrical element and a first one of the package terminals, and forming a third electrical connection between a second one of the package terminals and a second one of the lower contact pads via the interposer.

Patent Agency Ranking