公开(公告)号：US09805790B2

公开(公告)日：2017-10-31

申请号：US15025229

申请日：2013-12-05

Applicant: Intel Corporation

Inventor： Nathaniel J. August ,  Pulkit Jain ,  Stefan Rusu ,  Fatih Hamzaoglu ,  Rangharajan Venkatesan ,  Muhammad Khellah ,  Charles Augustine ,  Carlos Tokunaga ,  James W. Tschanz ,  Yih Wang

IPC: G11C13/00 ,  G11C14/00 ,  G11C11/16

CPC classification number: G11C13/0061 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0011 ,  G11C13/0014 ,  G11C14/0081 ,  G11C14/009

Abstract: Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.

公开(公告)号：US11908542B2

公开(公告)日：2024-02-20

申请号：US16725747

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Somnath Paul ,  Turbo Majumder ,  Iqbal Rajwani ,  Andrew Lines ,  Altug Koker ,  Lakshminarayanan Striramassarma ,  Muhammad Khellah

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/22

CPC classification number: G11C7/1048 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22

Abstract: Prior knowledge of access pattern is leveraged to improve energy dissipation for general matrix operations. This improves memory access energy for a multitude of applications such as image processing, deep neural networks, and scientific computing workloads, for example. In some embodiments, prior knowledge of access pattern allows for burst read and/or write operations. As such, burst mode solution can provide energy savings in both READ (RD) and WRITE (WR) operations. For machine learning or inference, the weight values are known ahead in time (e.g., inference operation), and so the unused bytes in the cache line are exploited to store a sparsity map that is used for disabling read from either upper or lower half of the cache line, thus saving dynamic capacitance.

公开(公告)号：US20210043251A1

公开(公告)日：2021-02-11

申请号：US17001432

申请日：2020-08-24

Applicant: Intel Corporation

Inventor： Muhammad M. Khellah ,  Somnath Paul ,  Charles Augustine ,  Turbo Majumder ,  Suyoung Bang

IPC: G11C11/419 ,  G11C11/412 ,  G11C7/12 ,  G11C7/10 ,  G11C11/418

Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.

公开(公告)号：US10755771B2

公开(公告)日：2020-08-25

申请号：US16226385

申请日：2018-12-19

Applicant: Intel Corporation

Inventor： Muhammad M. Khellah ,  Somnath Paul ,  Charles Augustine ,  Turbo Majumder ,  Suyoung Bang

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/419 ,  G11C11/412 ,  G11C7/12 ,  G11C7/10 ,  G11C11/418 ,  G11C7/22

Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.

公开(公告)号：US10665222B2

公开(公告)日：2020-05-26

申请号：US16022376

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Suyoung Bang ,  Muhammad Khellah ,  Somnath Paul ,  Charles Augustine ,  Turbo Majumder ,  Wootaek Lim ,  Tobias Bocklet ,  David Pearce

IPC: G01L15/00 ,  G10L15/02 ,  G10L25/03 ,  G10L15/20 ,  G10L25/24 ,  G10L25/18 ,  G10L25/09

Abstract: A system, article, and method provide temporal-domain feature extraction for automatic speech recognition.

公开(公告)号：US10374584B1

公开(公告)日：2019-08-06

申请号：US15916130

申请日：2018-03-08

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Muhammad Khellah ,  Arvind Raman ,  Feroze Merchant ,  Ashish Choubal

IPC: H03K3/037 ,  G01R31/3185

Abstract: An apparatus comprising: a flip-flip comprising a master stage and a slave stage, wherein the slave stage is coupled to the master stage, wherein the master and slave stages are coupled to a first power supply rail; and a scan circuitry coupled to the slave stage of the flip-flip, wherein at least a portion of the scan circuitry is coupled to a second power supply rail.

公开(公告)号：US20190115011A1

公开(公告)日：2019-04-18

申请号：US15786803

申请日：2017-10-18

Applicant: Intel Corporation

Inventor： Muhammad Khellah ,  Oren Arad ,  Binuraj Ravindran ,  Somnath Paul ,  Charles Augustine ,  Bruno Umbria Pedroni

IPC: G10L15/02 ,  G10L25/30 ,  G10L15/06 ,  G06N3/04

CPC classification number: G10L15/02 ,  G06N3/049 ,  G10L15/063 ,  G10L15/16 ,  G10L25/12 ,  G10L25/24 ,  G10L25/30 ,  G10L2015/0635 ,  G10L2015/088

Abstract: An example apparatus for detecting keywords in audio includes an audio receiver to receive audio comprising a keyword to be detected. The apparatus also includes a spike transducer to convert the audio into a plurality of spikes. The apparatus further includes a spiking neural network to receive one or more of the spikes and generate a spike corresponding to a detected keyword.

公开(公告)号：US09916884B2

公开(公告)日：2018-03-13

申请号：US15115461

申请日：2014-03-07

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Carlos Tokunaga ,  James W. Tschanz

IPC: G11C11/16 ,  H03M1/12 ,  G11C13/00

CPC classification number: G11C11/1695 ,  G06F21/34 ,  G06F21/73 ,  G06F21/79 ,  G09C1/00 ,  G11C7/16 ,  G11C7/24 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0059 ,  G11C2013/0045 ,  G11C2013/005 ,  H03M1/12 ,  H03M1/124 ,  H04L9/0866

Abstract: Described is a physically unclonable functional circuit comprising: a resistive memory device (e.g., an MTJ device) having at least two terminals; a transistor coupled to one of the at least two terminals of the resistive memory device; and an analog-to-digital converter (ADC) having an input coupled to the one of the at least two terminals of the resistive memory device.

公开(公告)号：US20170365313A1

公开(公告)日：2017-12-21

申请号：US15631373

申请日：2017-06-23

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Somnath Paul ,  Sadique Ul Ameen Sheik ,  Muhammad M. Khellah

IPC: G11C11/16 ,  G06N5/02

CPC classification number: G11C11/161 ,  G06N3/049 ,  G06N3/0635 ,  G06N3/088 ,  G06N5/025 ,  G11C11/1653 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/54 ,  G11C13/0002

Abstract: Embodiments include apparatuses, systems, and methods including a memory apparatus including a plurality of bit cells, wherein each of the plurality of bit cells correspond to a respective weight value and include a switch device that has a magnetic tunnel junction (MTJ) or other suitable resistive memory element to produce stochastic switching. In embodiments, the switch device may produce a switching output according to a stochastic switching probability of the switch device. In embodiments, a bit line or a source line passes a current across the MTJ for a switching time associated with the stochastic switching probability to produce the switching output which enables a determination of whether the respective weight value is to be updated. Other embodiments may also be described and claimed.

公开(公告)号：US09722606B2

公开(公告)日：2017-08-01

申请号：US15331280

申请日：2016-10-21

Applicant: INTEL CORPORATION

Inventor： Arijit Raychowdhury ,  Charles Augustine ,  James W. Tschanz ,  Vivek K. De

IPC: G05F1/10 ,  G05F1/59 ,  H03K19/00 ,  G05F1/46 ,  G06F1/32 ,  H03K3/037

CPC classification number: H03K19/0016 ,  G05F1/10 ,  G05F1/461 ,  G05F1/59 ,  G06F1/3287 ,  G06F1/3296 ,  H03K3/0377 ,  H03K19/0008

Abstract: Described is an apparatus which comprises: a clamp coupled between a first power supply and a second power supply, the clamp including a plurality of transistors, a circuit to operate with the second power supply; and a control unit to turn on and off the plurality of transistors to adjust the second power supply when the apparatus enters a low power mode. The control unit includes a first comparator to compare the second power supply with a first reference, a second comparator to compare the second power supply with a second reference, and a counter. The counter counts up when the second power supply is higher than the first reference and counts down when the second power supply is lower than the second reference.