中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

40 records (took 0.019 seconds)

    COMPUTE NEAR MEMORY WITH BACKEND MEMORY
    21.
    发明申请
    COMPUTE NEAR MEMORY WITH BACKEND MEMORY 审中-公开

    公开(公告)号：US20200279850A1

    公开(公告)日：2020-09-03

    申请号：US16827542

    申请日：2020-03-23

    Applicant: Intel Corporation

    Inventor： Abhishek SHARMA ,  Noriyuki SATO ,  Sarah ATANASOV ,  Huseyin Ekin SUMBUL ,  Gregory K. CHEN ,  Phil KNAG ,  Ram KRISHNAMURTHY ,  Hui Jae YOO ,  Van H. LE

    IPC: H01L27/108 ,  H01L27/12 ,  G11C11/4096

    Abstract: Examples herein relate to a memory device comprising an eDRAM memory cell, the eDRAM memory cell can include a write circuit formed at least partially over a storage cell and a read circuit formed at least partially under the storage cell; a compute near memory device bonded to the memory device; a processor; and an interface from the memory device to the processor. In some examples, circuitry is included to provide an output of the memory device to emulate output read rate of an SRAM memory device comprises one or more of: a controller, a multiplexer, or a register. Bonding of a surface of the memory device can be made to a compute near memory device or other circuitry. In some examples, a layer with read circuitry can be bonded to a layer with storage cells. Any layers can be bonded together using techniques described herein.

    BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES
    25.
    发明申请
    BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220352032A1

    公开(公告)日：2022-11-03

    申请号：US17866122

    申请日：2022-07-15

    Applicant: INTEL CORPORATION

    Inventor： Aaron D. LILAK ,  Ehren MANNEBACH ,  Anh PHAN ,  Richard E. SCHENKER ,  Stephanie A. BOJARSKI ,  Willy RACHMADY ,  Patrick R. MORROW ,  Jeffrey D. BIELEFELD ,  Gilbert DEWEY ,  Hui Jae YOO

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L23/532 ,  H01L23/48

    Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

    CONFORMAL LOW TEMPERATURE HERMETIC DIELECTRIC DIFFUSION BARRIERS
    26.
    发明申请
    CONFORMAL LOW TEMPERATURE HERMETIC DIELECTRIC DIFFUSION BARRIERS 有权

    公开(公告)号：US20220344201A1

    公开(公告)日：2022-10-27

    申请号：US17855656

    申请日：2022-06-30

    Applicant: Intel Corporation

    Inventor： Sean KING ,  Hui Jae YOO ,  Sreenivas KOSARAJU ,  Timothy GLASSMAN

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L23/00

    Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.

    THREE DIMENSIONAL INTEGRATED CIRCUITS WITH STACKED TRANSISTORS
    28.
    发明申请
    THREE DIMENSIONAL INTEGRATED CIRCUITS WITH STACKED TRANSISTORS 审中-公开

    公开(公告)号：US20200211905A1

    公开(公告)日：2020-07-02

    申请号：US16236156

    申请日：2018-12-28

    Applicant: Intel Corporation

    Inventor： Cheng-Ying HUANG ,  Willy RACHMADY ,  Gilbert DEWEY ,  Aaron LILAK ,  Kimin JUN ,  Brennen MUELLER ,  Ehren MANNEBACH ,  Anh PHAN ,  Patrick MORROW ,  Hui Jae YOO ,  Jack T. KAVALIEROS

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423

    Abstract: Embodiments herein describe techniques for a semiconductor device including a first transistor stacked above and self-aligned with a second transistor, where a shadow of the first transistor substantially overlaps with the second transistor. The first transistor includes a first gate electrode, a first channel layer including a first channel material and separated from the first gate electrode by a first gate dielectric layer, and a first source electrode coupled to the first channel layer. The second transistor includes a second gate electrode, a second channel layer including a second channel material and separated from the second gate electrode by a second gate dielectric layer, and a second source electrode coupled to the second channel layer. The second source electrode is self-aligned with the first source electrode, and separated from the first source electrode by an isolation layer. Other embodiments may be described and/or claimed.

    CONFORMAL LOW TEMPERATURE HERMETIC DIELECTRIC DIFFUSION BARRIERS
    29.
    发明申请
    CONFORMAL LOW TEMPERATURE HERMETIC DIELECTRIC DIFFUSION BARRIERS 审中-公开

    公开(公告)号：US20190371658A1

    公开(公告)日：2019-12-05

    申请号：US16538666

    申请日：2019-08-12

    Applicant: Intel Corporation

    Inventor： Sean KING ,  Hui Jae YOO ,  Sreenivas KOSARAJU ,  Timothy GLASSMAN

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L23/00

    Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.

Patent Agency Ranking