公开(公告)号：US10025737B2

公开(公告)日：2018-07-17

申请号：US14731183

申请日：2015-06-04

Applicant: Intel Corporation

Inventor： Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Robert W. Faber

IPC: G06F13/28 ,  G06F13/16 ,  G06F12/02 ,  G06F13/42 ,  G11C7/22 ,  G06F1/12 ,  G06F13/40 ,  G06F13/38 ,  H04L5/00 ,  H04L7/00

Abstract: A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.

公开(公告)号：US20180088834A1

公开(公告)日：2018-03-29

申请号：US15281006

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Rajesh Sundaram ,  Albert Fazio ,  Derchang Kau ,  Shekoufeh Qawami

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/0238 ,  G06F12/0246 ,  G06F13/16 ,  G06F13/1657 ,  G11C13/0004

Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.

公开(公告)号：US09916104B2

公开(公告)日：2018-03-13

申请号：US15344809

申请日：2016-11-07

Applicant: Intel Corporation

Inventor： Sowmiya Jayachandran ,  Rajesh Sundaram ,  Robert Faber

IPC: G11C5/14 ,  G06F3/06

CPC classification number: G06F3/0625 ,  G06F1/3275 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/02 ,  G11C5/147 ,  G11C5/148 ,  G11C7/00 ,  Y02D10/14

Abstract: Examples are given for techniques for entry to a lower power state for a memory device or die. The examples to include delaying transitions of the memory device or die from a first higher consuming power state to a second relatively lower power state using one or more programmable counters maintained at or with the memory device.

公开(公告)号：US09721657B1

公开(公告)日：2017-08-01

申请号：US15089507

申请日：2016-04-02

Applicant: Intel Corporation

Inventor： Shekoufeh Qawami ,  Rajesh Sundaram ,  Prashant S. Damle ,  Doyle Rivers ,  Julie M. Walker

IPC: G11C13/00

CPC classification number: G11C13/0033 ,  G06F13/1668 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069

Abstract: Apparatus, systems, and methods to correct for threshold voltage drift in non-volatile memory devices are disclosed and described. In one example, a compensated demarcation voltage is generated by either a time-based drift compensation scheme or a disturb-based drift compensation scheme, and read and write operations to the non-volatile memory are carried out using the compensated voltage threshold.

公开(公告)号：US11182242B2

公开(公告)日：2021-11-23

申请号：US16448126

申请日：2019-06-21

Applicant: Intel Corporation

Inventor： Chetan Chauhan ,  Wei Wu ,  Rajesh Sundaram ,  Shigeki Tomishima

IPC: G06F11/30 ,  G06F11/10 ,  G06F11/07

Abstract: Technologies for preserving error correction capability in compute-in-memory operations in a memory include memory media and a media access circuitry coupled with the memory media. The media access circuitry is to detect an error code adjustment state indicative of a failure in the initiated error correction. The media access circuitry is to adjust a voltage to the memory media to eliminate the error code correction adjustment state. Once eliminated, the media access circuitry is to perform the error correction on the read data.

公开(公告)号：US11023320B2

公开(公告)日：2021-06-01

申请号：US16375362

申请日：2019-04-04

Applicant: Intel Corporation

Inventor： Wei Wu ,  Rajesh Sundaram ,  Chetan Chauhan ,  Jawad B. Khan ,  Shigeki Tomishima ,  Srikanth Srinivasan

IPC: G06F11/10 ,  G06F3/06 ,  G06F11/22

Abstract: Technologies for providing multiple levels of error correction include a memory that includes media access circuitry coupled to a memory media. The media access circuitry is to read data from the memory media. Additionally, the media access circuitry is to perform, with an error correction logic unit located in the media access circuitry, error correction on the read data to produce error-corrected data.

公开(公告)号：US20200301828A1

公开(公告)日：2020-09-24

申请号：US16894180

申请日：2020-06-05

Applicant: Intel Corporation

Inventor： Jawad Khan ,  Chetan Chauhan ,  Rajesh Sundaram ,  Sourabh Dongaonkar ,  Sandeep Guliani ,  Dipanjan Sengupta ,  Mariano Tepper

IPC: G06F12/06 ,  G06F12/02 ,  G06F13/40

Abstract: Technologies for column reads for clustered data include a device having a column-addressable memory and circuitry connected to the memory. The column-addressable memory includes multiple dies. The circuitry may be configured to determine multiple die offsets based on a logical column number of the data cluster, determine a base address based on the logical column number, program the dies with the die offsets. The circuitry is further to read logical column data from the column-addressable memory. To read the data, each die adds the corresponding die offset to the base address. The column-addressable memory may include multiple command/address buses. The circuitry may determine a starting address for each of multiple logical columns and issue a column read for each starting address via a corresponding command/address bus. Other embodiments are described and claimed.

公开(公告)号：US20200265098A1

公开(公告)日：2020-08-20

申请号：US16870003

申请日：2020-05-08

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Dipanjan Sengupta ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Jawad Khan ,  Theodore Willke ,  Richard Coulson ,  Rajesh Sundaram

IPC: G06F16/903 ,  G06K9/62 ,  G06F17/16

Abstract: Technologies for performing stochastic similarity searches in an online clustering space include a device having a column addressable memory and circuitry. The circuitry is configured to determine a Hamming distance from a binary dimensionally expanded vector to each cluster of a set of clusters of binary dimensionally expanded vectors in the memory, identify the cluster having the smallest Hamming distance from the binary dimensionally expanded vector, determine whether the identified cluster satisfies a target size, and add or delete, in response to a determination that the identified cluster does not satisfy the target size, the binary dimensionally expanded vector to or from the identified cluster.

公开(公告)号：US20190266219A1

公开(公告)日：2019-08-29

申请号：US16411730

申请日：2019-05-14

Applicant: Intel Corporation

Inventor： Chetan Chauhan ,  Rajesh Sundaram ,  Richard Coulson ,  Bruce Querbach ,  Jawad B. Khan ,  Shigeki Tomishima ,  Srikanth Srinivasan

IPC: G06F17/16 ,  G06F7/78 ,  G06F9/38 ,  G06F9/30

Abstract: Technologies for performing in-memory macro operations include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory macro operation indicative of a set of multiple in-memory operations. The media access circuitry is also to perform, in response to the request, the in-memory macro operation on data present in the memory media.

公开(公告)号：US09136873B2

公开(公告)日：2015-09-15

申请号：US13792597

申请日：2013-03-11

Applicant: Intel Corporation

Inventor： Kiran Pangal ,  Prashant S. Damle ,  Rajesh Sundaram ,  Shekoufeh Qawami ,  Julie M. Walker ,  Doyle Rivers

IPC: H03M13/00 ,  H03M13/05 ,  H03M13/27 ,  G06F11/10 ,  H03M13/15 ,  H03M13/19

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  H03M13/05 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/27 ,  H03M13/6508

Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.

Abstract translation: 可以通过确定一组存储器阵列的逻辑阵列地址并且至少部分地基于该组内的至少两个存储器阵列的逻辑位置将逻辑阵列地址变换为至少两个唯一阵列地址来减少不可校正的存储器错误 的存储器阵列。 然后使用至少两个唯一的阵列地址分别访问至少两个存储器阵列。