公开(公告)号：US20190386007A1

公开(公告)日：2019-12-19

申请号：US16452469

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Peter L.D. CHANG ,  Uygar E. AVCI ,  David KENCKE ,  Ibrahim BAN

IPC: H01L27/108 ,  H01L29/51 ,  H01L29/16 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/12

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US20190035790A1

公开(公告)日：2019-01-31

申请号：US16151175

申请日：2018-10-03

Applicant: Intel Corporation

Inventor： Peter L.D. CHANG ,  Uygar E. AVCI ,  David KENCKE ,  Ibrahim BAN

IPC: H01L27/108 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L29/16 ,  H01L29/06 ,  H01L27/12 ,  H01L27/092

CPC classification number: H01L27/10802 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L27/0928 ,  H01L27/108 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7851 ,  Y10S257/903

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US20190034360A1

公开(公告)日：2019-01-31

申请号：US15660819

申请日：2017-07-26

Applicant: Intel Corporation

Inventor： Kaushik VAIDYANATHAN ,  Daniel H. MORRIS ,  Uygar E. AVCI ,  Ian A. YOUNG ,  Tanay KARNIK ,  Huichu LIU

IPC: G06F13/10 ,  G06F9/445 ,  G06F1/26

Abstract: Described is an apparatus which comprises: a first electrical path comprising at least one driver and receiver; and a second electrical path comprising at least one driver and receiver, wherein the first and second electrical paths are to receive a same input signal, wherein the first electrical path and the second electrical path are parallel to one another and have substantially the same propagation delays, and wherein the second electrical path is enabled during a first operation mode and disabled during a second operation mode.

公开(公告)号：US20180226478A1

公开(公告)日：2018-08-09

申请号：US15747719

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Uygar E. AVCI ,  David L. KENCKE ,  Patrick MORROW ,  Kerryann FOLEY ,  Stephen M. CEA ,  Rishabh MEHANDRU

IPC: H01L29/417 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/785

Abstract: Techniques and mechanisms to provide insulation for a component of an integrated circuit device. In an embodiment, structures of a circuit component are formed in or on a first side of a semiconductor substrate, the structures including a first doped region, a second doped region and a third region between the first doped region and the second doped region. The substrate has formed therein an insulation structure, proximate to the circuit component structures, which is laterally constrained to extend only partially from a location under the circuit component toward an edge of the substrate. In another embodiment, a second side of the substrate—opposite the first side—is exposed by thinning to form the substrate from a wafer. Such thinning enables subsequent back side processing to form a recess in the second side, and to deposit the insulation structure in the recess.

公开(公告)号：US20170054006A1

公开(公告)日：2017-02-23

申请号：US15118843

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： Uygar E. AVCI ,  Roza KOTLYAR ,  Ian A. YOUNG

IPC: H01L29/66 ,  H01L23/66 ,  G06F3/041 ,  H01L29/786

CPC classification number: H01L29/66977 ,  G06F3/041 ,  H01L21/18 ,  H01L23/66 ,  H01L29/165 ,  H01L29/205 ,  H01L29/42312 ,  H01L29/66356 ,  H01L29/66742 ,  H01L29/7391 ,  H01L29/78 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78696 ,  H01L29/88 ,  H01L2223/6677

Abstract: Described is a tunneling field effect transistor (TFET), comprising: a drain region having a first conductivity type; a source region having a second conductivity type opposite of the first conductivity type; a gate region to cause formation of a channel region between the source and drain regions; and a pocket disposed near a junction of the source region, wherein the pocket region formed from a material having lower percentage of one type of atom than percentage of the one type of atom in the source, channel, and drain regions.

Abstract translation: 描述了隧道场效应晶体管（TFET），其包括：具有第一导电类型的漏极区; 源区域，具有与第一导电类型相反的第二导电类型; 栅极区域，用于在源区和漏区之间形成沟道区; 以及设置在所述源极区域的接合点附近的口袋，其中所述口袋区域由具有比所述源极，沟道和漏极区域中的一种类型的原子的百分比低的一种类型的原子的比例低的材料形成。

公开(公告)号：US20160373108A1

公开(公告)日：2016-12-22

申请号：US15122150

申请日：2014-03-27

Applicant: INTEL CORPORATION

Inventor： Daniel H. MORRIS ,  Uygar E. AVCI ,  Rafael RIOS ,  Ian A. YOUNG

IPC: H03K17/693 ,  H01L29/775 ,  G11C5/06 ,  H01L27/092

CPC classification number: H03K17/693 ,  G11C5/066 ,  H01L27/092 ,  H01L29/7391 ,  H01L29/775 ,  H03K19/094 ,  H03K19/0948

Abstract: Multiplexor circuits with Tunneling field effect transistors (TFET) devices are described. For example, a multiplexor circuit includes a first set of tunneling field effect transistor (TFET) devices that are coupled to each other. The first set of TFET devices receive a first data input signal, a first select signal, and a second select signal. A second set of TFET devices are coupled to each other and receive a second data input signal, the first select signal, and the second select signal. An output terminal is coupled to the first and second set of TFETs. The output terminal generates an output signal of the multiplexor circuit.

Abstract translation: 描述了具有隧道场效应晶体管（TFET）器件的多路复用器电路。 例如，多路复用器电路包括彼此耦合的第一组隧道场效应晶体管（TFET）器件。 第一组TFET器件接收第一数据输入信号，第一选择信号和第二选择信号。 第二组TFET器件彼此耦合并且接收第二数据输入信号，第一选择信号和第二选择信号。 输出端子耦合到第一和第二组TFET。 输出端产生多路复用器电路的输出信号。

公开(公告)号：US20230420514A1

公开(公告)日：2023-12-28

申请号：US17852016

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Chelsey DOROW ,  Sudarat LEE ,  Kevin P. O'BRIEN ,  Ande KITAMURA ,  Ashish Verma PENUMATCHA ,  Carl H. NAYLOR ,  Kirby MAXEY ,  Scott B. CLENDENNING ,  Uygar E. AVCI ,  Chia-Ching LIN

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/18 ,  H01L29/786 ,  H01L29/778

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/18 ,  H01L29/78696 ,  H01L29/778

Abstract: Embodiments disclosed herein include transistor devices. In an embodiment, the transistor comprises a transition metal dichalcogenide (TMD) channel. In an embodiment, a two dimensional (2D) dielectric is over the TMD channel. In an embodiment, a gate metal is over the 2D dielectric.

公开(公告)号：US20230411443A1

公开(公告)日：2023-12-21

申请号：US18129258

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Kaan OGUZ ,  Chia-Ching LIN ,  Arnab SEN GUPTA ,  I-Cheng TUNG ,  Sou-Chi CHANG ,  Sudarat LEE ,  Matthew V. METZ ,  Uygar E. AVCI ,  Scott B. CLENDENNING ,  Ian A. YOUNG

IPC: H01L21/02 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L28/56 ,  H01L28/92 ,  H01L28/91 ,  H01L28/75 ,  H01L23/5223 ,  H01L23/5226 ,  H01L24/32 ,  H01L28/65 ,  H01L2224/32225 ,  H01L24/73 ,  H01L2224/16227 ,  H01L24/16 ,  H01L2224/73204

Abstract: Metal insulator metal capacitors are described. In an example, a metal-insulator-metal (MIM) capacitor includes a first electrode. An insulator is over the first electrode. The insulator includes a first layer, and a second layer over the first layer. The first layer has a leakage current that is less than a leakage current of the second layer. The second layer has a dielectric constant that is greater than a dielectric constant of the first layer. A second electrode is over the insulator.

公开(公告)号：US20230100860A1

公开(公告)日：2023-03-30

申请号：US17485306

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Sou-Chi CHANG ,  Nazila HARATIPOUR ,  Shriram SHIVARAMAN ,  Uygar E. AVCI ,  Sarah ATANASOV ,  Christopher M. NEUMANN

IPC: H01L27/11507 ,  H01L27/108 ,  H01L25/065

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to memory devices utilizing dead-layer-free materials to reduce disturb effects. Other embodiments may be described or claimed.

公开(公告)号：US20230100505A1

公开(公告)日：2023-03-30

申请号：US17485238

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Ashish Verma PENUMATCHA ,  Sarah ATANASOV ,  Seung Hoon SUNG ,  Rahul RAMAMURTHY ,  I-Cheng TUNG ,  Uygar E. AVCI ,  Matthew V. METZ ,  Jack T. KAVALIEROS ,  Chia-Ching LIN ,  Kaan OGUZ

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/66

Abstract: Embodiments disclosed herein include transistor devices and methods of forming such devices. In an embodiment, a transistor device comprises a first channel, wherein the first channel comprises a semiconductor material and a second channel above the first channel, wherein the second channel comprises the semiconductor material. In an embodiment, a first spacer is between the first channel and the second channel, and a second spacer is between the first channel and the second channel. In an embodiment, a first gate dielectric is over a surface of the first channel that faces the second channel, and a second gate dielectric is over a surface of the second channel that faces the first channel. In an embodiment, the first gate dielectric is physically separated from the second gate dielectric.