Abstract:
A laminating structure includes a first magnetic layer, a second magnetic layer, a first spacer disposed between the first and second magnetic layers and a second spacer disposed on the second magnetic layer.
Abstract:
A switching power supply in an integrated circuit, an integrated circuit comprising a switching power supply, and a method of assembling a switching power supply in an integrated circuit are disclosed. In one embodiment, the invention provides a three-dimensional switching power supply in an integrated circuit comprising a device layer. The switching power supply comprises three distinct strata arranged in series with the device layer, the three distinct strata including a switching layer including switching circuits, a capacitor layer including banks of capacitors, and an inductor layer including inductors. This switching power supply further comprises a multitude of connectors electrically and mechanically connecting together the device layer, the switching layer, the capacitor layer, and the inductor layer. The switching circuits, the capacitors and the inductors form a switching power supply for supplying power to the device layer.
Abstract:
A semiconductor article which includes a semiconductor base portion including a semiconductor material; a back end of the line (BEOL) wiring portion on the semiconductor base portion and comprising a plurality of wiring layers having metallic wiring and insulating material, said BEOL wiring portion excluding a semiconductor material; and a guard ring in the BEOL wiring portion and surrounding a structure in the semiconductor chip, the guard ring having a zig-zag configuration.
Abstract:
Through-via structures and methods of their formation are disclosed. In one such method, a first etch through at least a first dielectric material of a wiring layer is performed such that a first hole outlining a collar structure for the through-via is formed. In addition, a stress-abating dielectric material is deposited in the hole such that the stress-abating dielectric material is disposed at least laterally from the first dielectric material. Further, a second etching through at least a semiconductor material of a semiconductor layer that is disposed below the wiring layer is performed, where the second etching forms a via hole in the semiconductor material. Additionally, at least a portion of the via hole is filled with conductive material to form the through-via such that the stress-abating dielectric material, at least in the wiring layer, provides a buffer between the conductive material and the first dielectric material.
Abstract:
Through-via structures and methods of their formation are disclosed. One such structure includes a conductor structure, a dielectric via lining and a stress-abating dielectric material. The conductor structure is formed of conducting material extending through a wiring layer of a semiconductor device and through a semiconductor layer below the wiring layer. Here, the wiring layer of the semiconductor device includes a first dielectric material. The dielectric via lining extends along the conductor structure at least in the semiconductor layer. Further, the stress-abating dielectric material is disposed between the conductor structure and the first dielectric material in at least the wiring layer, where the stress-abating dielectric material is disposed over portions of the semiconductor layer that are outside outer boundaries of the via lining.
Abstract:
A laminating structure includes a first magnetic layer, a second magnetic layer, a first spacer disposed between the first and second magnetic layers and a second spacer disposed on the second magnetic layer.
Abstract:
Disclosed herein are through silicon vias (TSVs) and contacts formed on a semiconductor material, methods of manufacturing, and design structures. The method includes forming a contact hole in a dielectric material formed on a substrate. The method further includes forming a via in the substrate and through the dielectric material. The method further includes lining the contact hole and the dielectric material with a metal liner using a deposition technique that will avoid formation of the liner in the via formed in the substrate. The method further includes filling the contact hole and the via with a metal such that the metal is formed on the liner in the contact hole and directly on the substrate in the via.
Abstract:
A magnetic device according to one embodiment includes a source of flux; a magnetic pole having two or more gaps; and a low reluctance path positioned towards at least one of the gaps and riot positioned towards at least one other of the gaps for affecting a magnetic field formed at the at least one of the gaps when the source of flux is generating flux. Other disclosed embodiments include devices having coil turns with a non-uniform placement in the magnetic yoke for altering a magnetic field formed at the at least one of the gaps during writing. In further embodiments, a geometry of the magnetic pole near or at one of the gaps is different than a geometry of the magnetic pole near or at another of the gaps to help equalize fields formed at the gaps when the source of flux is generating flux.
Abstract:
A magnetic device according to one embodiment includes a source of flux; a magnetic pole coupled to the source of flux, the magnetic pole having two or more gaps; and a low reluctance path positioned towards at least one of the gaps and not positioned towards at least one other of the gaps for affecting a magnetic field formed at the at least one of the gaps when the source of flux is generating flux. Other disclosed embodiments include devices having coil turns with a non-uniform placement in the magnetic yoke for altering a magnetic field formed at the at least one of the gaps during writing. In further embodiments, a geometry of the magnetic pole near or at one of the gaps is different than a geometry of the magnetic pole near or at another of the gaps to help equalize fields formed at the gaps when the source of flux is generating flux.
Abstract:
A method and apparatus for bonding a processor wafer with a microchannel wafer/glass manifold to form a bonded wafer structure are provided. A glass fixture is also provided for protecting C4 solder bumps on chips disposed on the processor wafer. When the glass fixture is positioned on the processor wafer, posts extending from the glass fixture contact corresponding regions on the processor wafer devoid of C4 solder bumps, so that the glass fixture protects the C4 solder bumps during wafer bonding. The method involves positioning the processor wafer/glass fixture and the microchannel wafer/glass manifold in a metal fixture having one or more alignment structures adapted to engage corresponding alignment elements formed in the processor wafer, glass fixture and/or glass manifold. The metal fixture secures the wafer components in place and, after melting solder pellets disposed between the processor wafer/glass fixture and microchannel wafer/glass manifold, a bonded wafer structure is formed.