公开(公告)号：US20210225705A1

公开(公告)日：2021-07-22

申请号：US16744456

申请日：2020-01-16

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Cheng Chi ,  Chih-Chao Yang ,  Kangguo Cheng

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L21/285

Abstract: A back end of line interconnect structure and methods for forming the interconnect structure including a self-aligned via generally includes a subtractive etch process to define the vias. The vias include a via core and a liner to provide a critical dimension equal to a critical dimension of an underlying metal line. The metal lines are free of the liner. The method provides some via metal liner material on top of metal lines that do not includes a via in direct contact therewith.

公开(公告)号：US10658459B2

公开(公告)日：2020-05-19

申请号：US16545867

申请日：2019-08-20

Applicant: International Business Machines Corporation

Inventor： Robin Hsin Kuo Chao ,  Kangguo Cheng ,  Cheng Chi ,  Ruilong Xie ,  John H. Zhang

IPC: H01L29/06 ,  H01L29/775 ,  H01L29/66

Abstract: A substrate structure for a nanosheet transistor includes a plurality of nanosheet layers and a plurality of recesses between the nanosheet layers. The substrate structure includes at least one trench through portions of the nanosheet layers, the sacrificial layers, and the substrate. The substrate structure includes a u-shaped portion formed at a bottom portion of the at least one trench. The u-shaped portion includes a bottom cavity. The substrate structure further includes a first liner disposed upon the u-shaped portion of the at least one trench, and a second liner disposed on the first liner. The substrate structure further includes a third liner disposed within the at least one trench to fill the bottom cavity of the u-shaped portion to form a bottom inner spacer within the bottom cavity.

公开(公告)号：US10431651B1

公开(公告)日：2019-10-01

申请号：US15967524

申请日：2018-04-30

Applicant: International Business Machines Corporation

Inventor： Robin Hsin Kuo Chao ,  Kangguo Cheng ,  Cheng Chi ,  Ruilong Xie ,  John H. Zhang

IPC: H01L29/06 ,  H01L29/775 ,  H01L29/66

Abstract: A substrate structure for a nanosheet transistor includes a plurality of nanosheet layers and a plurality of recesses between the nanosheet layers. The substrate structure includes at least one trench through portions of the nanosheet layers, the sacrificial layers, and the substrate. The substrate structure includes a u-shaped portion formed at a bottom portion of the at least one trench. The u-shaped portion includes a bottom cavity. The substrate structure further includes a first liner disposed upon the u-shaped portion of the at least one trench, and a second liner disposed on the first liner. The substrate structure further includes a third liner disposed within the at least one trench to fill the bottom cavity of the u-shaped portion to form a bottom inner spacer within the bottom cavity.

公开(公告)号：US10340179B2

公开(公告)日：2019-07-02

申请号：US15703097

申请日：2017-09-13

Applicant: International Business Machines Corporation

Inventor： Cheng Chi ,  Kafai Lai ,  Chi-Chun Liu ,  Yongan Xu

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/768

Abstract: A method of forming an interconnect element includes forming a trench in a dielectric material. The trench has a width equal to twice a natural pitch of a block copolymer. The block copolymer includes a first polymer and a second polymer. The method includes filling the trench with the block copolymer.

公开(公告)号：US10242881B2

公开(公告)日：2019-03-26

申请号：US15813518

申请日：2017-11-15

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Cheng Chi ,  Chi-Chun Liu ,  Peng Xu

IPC: H01L21/30 ,  H01L29/66 ,  H01L21/31 ,  H01L21/308 ,  H01L21/311 ,  H01L21/033

Abstract: A method of forming a semiconductor device and resulting structures having a dummy semiconductor fin removed from within an array of tight pitch semiconductor fins by forming a first spacer including a first material on a substrate; forming a second spacer including a second material on the substrate, the second spacer adjacent to the first spacer; and applying an etch process to the first spacer and the second spacer; wherein the etch process removes the first spacer at a first etch rate; wherein the etch process removes the second spacer at a second etch rate; wherein the first etch rate is different than the second etch rate.

公开(公告)号：US10090410B1

公开(公告)日：2018-10-02

申请号：US15462175

申请日：2017-03-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng Chi ,  Tenko Yamashita ,  Chen Zhang

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/161 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

Abstract: A method of forming a vertical transport fin field effect transistor and a long-channel field effect transistor on the same substrate, including, forming a recessed region in a substrate and a fin region adjacent to the recessed region, forming one or more vertical fins on the fin region, forming a long-channel pillar from the substrate in the recessed region, where the long-channel pillar is at a different elevation than the one or more vertical fins, forming two or more long-channel source/drain plugs on the long-channel pillar, forming a bottom source/drain plug in the fin region, where the bottom source/drain plug is below the one or more vertical fins, forming a gate structure on the long-channel pillar and a gate structure on the one or more vertical fins, and forming a top source/drain on the top surface of the one or more vertical fins.

公开(公告)号：US10084068B2

公开(公告)日：2018-09-25

申请号：US15631385

申请日：2017-06-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/22 ,  H01L29/49 ,  H01L29/08 ,  H01L29/51 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L29/66795 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/22 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

公开(公告)号：US09947548B2

公开(公告)日：2018-04-17

申请号：US15231979

申请日：2016-08-09

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Cheng Chi ,  Chi-chun Liu ,  Peng Xu

IPC: H01L21/31 ,  H01L21/30 ,  H01L21/46 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L21/3085 ,  H01L21/0337 ,  H01L21/31116 ,  H01L29/785

Abstract: A method of forming a semiconductor device and resulting structures having a dummy semiconductor fin removed from within an array of tight pitch semiconductor fins by forming a first spacer including a first material on a substrate; forming a second spacer including a second material on the substrate, the second spacer adjacent to the first spacer; and applying an etch process to the first spacer and the second spacer; wherein the etch process removes the first spacer at a first etch rate; wherein the etch process removes the second spacer at a second etch rate; wherein the first etch rate is different than the second etch rate.

公开(公告)号：US20180047575A1

公开(公告)日：2018-02-15

申请号：US15231979

申请日：2016-08-09

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Cheng Chi ,  Chi-chun Liu ,  Peng Xu

IPC: H01L21/308 ,  H01L21/311

CPC classification number: H01L21/3085 ,  H01L21/0337 ,  H01L21/31116 ,  H01L29/785

Abstract: A method of forming a semiconductor device and resulting structures having a dummy semiconductor fin removed from within an array of tight pitch semiconductor fins by forming a first spacer including a first material on a substrate; forming a second spacer including a second material on the substrate, the second spacer adjacent to the first spacer; and applying an etch process to the first spacer and the second spacer; wherein the etch process removes the first spacer at a first etch rate; wherein the etch process removes the second spacer at a second etch rate; wherein the first etch rate is different than the second etch rate.

公开(公告)号：US09810980B1

公开(公告)日：2017-11-07

申请号：US15426523

申请日：2017-02-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  TOKYO ELECTRON LIMITED

Inventor： Hongyun Cottle ,  Cheng Chi ,  Chi-Chun Liu ,  Kristin Schmidt

IPC: C03C15/00 ,  G03F7/00 ,  C30B1/04 ,  C30B29/58 ,  H01L21/027 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3105

CPC classification number: G03F7/0002 ,  B81C1/00031 ,  B81C1/00396 ,  B81C1/00531 ,  B81C2201/0149 ,  C09K13/00 ,  C30B1/04 ,  C30B7/005 ,  C30B29/58 ,  C30B33/08 ,  H01L21/02118 ,  H01L21/0271 ,  H01L21/302 ,  H01L21/31058 ,  H01L21/31133

Abstract: Graphoepitaxy directed self-assembly methods generally include grafting a conformal layer of a polymer brush onto a topographic substrate. A planarization material, which functions as a sacrificial material is coated onto the topographic substrate. The planarization material is etched back to a top surface of the topographic substrate, wherein the etch back removes the polymer brush from the top surfaces of the topographic substrate. The remaining portion of the polymer brush is protected by the remaining planarization material below the top surface of the topographic substrate, which can be removed with a solvent to provide the topographic substrate with a conformal polymer brush below the top surface of the topographic substrate. The substrate is then coated with a block copolymer and annealed to direct self-assembly of the block copolymer. The methods mitigate island and/or hole defect formation.