公开(公告)号：US20190068214A1

公开(公告)日：2019-02-28

申请号：US15690728

申请日：2017-08-30

Applicant: Infineon Technologies AG

Inventor： Ketan Dewan ,  Reinhard Kussian ,  Juergen Schaefer

IPC: H03M3/00

Abstract: A modulator including a delta-sigma modulation circuit having an order greater than 1, and configured to modulate an input signal into a Pulse Density Modulated (PDM) signal; and a Pad Asymmetric Compensation (PAC) circuit configured to linearize a relation between a magnitude of the input signal and a number of rise or fall transitions of the PDM signal by maximizing the number of rise or fall transitions of the PDM signal, and to output a modified PDM signal, wherein the linearized relation is for compensating for any offset in the PDM signal.

公开(公告)号：US20180101458A1

公开(公告)日：2018-04-12

申请号：US15288434

申请日：2016-10-07

Applicant: Infineon Technologies AG

Inventor： Varun Kumar ,  Sandeep Naduvalamane ,  Sumit Khandelwal ,  Puneetha Mukherjee ,  Juergen Schaefer

IPC: G06F11/22 ,  G06F9/445 ,  G06F9/44 ,  G06F11/27 ,  G06F15/78

CPC classification number: G06F11/2289 ,  G06F9/4411 ,  G06F9/44505 ,  G06F11/2236 ,  G06F11/2284 ,  G06F11/27 ,  G06F15/781

Abstract: Methods and systems for checking the integrity of a system on chip (SOC) are described. The SOC can include a controller and one or more registers. Register value(s) from the register(s) can be obtained at a first time to generate a first set of register values. Process(es) of the SOC are executed at a second time after the first time. Register values can again be obtained from the registers at a third time after the second time to generate a second set of register values. The first set of register values can be compared with the second set of register values. Based on the comparison, an operating mode of the SOC can be adjusted. The SOC integrity verification system and method can be used in safety and/or monitoring application(s), such as ASIL applications. For example, the system and method can be used in partial or fully autonomous (self-driving) automotive systems.

公开(公告)号：US09923750B2

公开(公告)日：2018-03-20

申请号：US15184114

申请日：2016-06-16

Applicant: Infineon Technologies AG

Inventor： Andre Roger ,  Romain Ygnace ,  Juergen Schaefer ,  Matthias Marquardt ,  Ljudmil Anastasov

IPC: H04L27/14 ,  H04L27/16 ,  H04L27/22 ,  H04L27/26 ,  H04L27/02 ,  H04L27/10

CPC classification number: H04L27/2697 ,  H04L27/0014 ,  H04L27/02 ,  H04L27/10 ,  H04L2027/0016 ,  H04L2027/0018 ,  H04L2027/0055

Abstract: A modulator operable to control an oscillator is described. The modulator can include a memory that stores oscillator control values and a bit streaming block. The bit streaming block can generate a bit stream based on the oscillator control values and transmit the bit stream to the oscillator to control an oscillation frequency of the oscillator. The modulator can also include a bit streaming loader (BSL). The BSL can receive one or more of the oscillator control values from the memory, generate one or more corresponding bit values based on the one or more of the oscillator control values, and provide the one or more bit values to the bit streaming block. The bit streaming block can then generate the bit stream based the one or more bit values generated by the BSL.

公开(公告)号：US09385059B2

公开(公告)日：2016-07-05

申请号：US14011772

申请日：2013-08-28

Applicant: Infineon Technologies AG

Inventor： Peter Ossimitz ,  Juergen Schaefer ,  Liu Chen ,  Markus Dinkel ,  Stefan Macheiner

IPC: H05K7/20 ,  H01L23/34 ,  H01L21/48 ,  H05K3/32 ,  H01L23/367 ,  H01L23/40 ,  H05K3/28 ,  H05K5/00 ,  H01L23/31 ,  H01L23/427 ,  H01L23/498 ,  H05K1/02

CPC classification number: H01L23/34 ,  H01L21/4882 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/4006 ,  H01L23/4093 ,  H01L23/427 ,  H01L23/49822 ,  H01L2023/405 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/13055 ,  H05K1/0206 ,  H05K1/0209 ,  H05K3/284 ,  H05K3/32 ,  H05K5/0034 ,  H05K7/20854 ,  H05K2201/10166 ,  Y10T29/49146 ,  H01L2924/00

Abstract: An electronic device comprises a substrate, at least one electronic chip mounted on and electrically connected to the substrate and being configured as a system control unit for controlling a connected system, a heat removal structure thermally connected to the at least one electronic chip and configured for removing heat generated by the at least one electronic chip upon operation of the electronic device, and an overmolding structure configured for at least partially encapsulating at least the at least one electronic chip and the substrate.

公开(公告)号：US20150062825A1

公开(公告)日：2015-03-05

申请号：US14011772

申请日：2013-08-28

Applicant: Infineon Technologies AG

Inventor： Peter Ossimitz ,  Juergen Schaefer ,  Liu Chen ,  Markus Dinkel ,  Stefan MacHeiner

IPC: H01L23/34 ,  H05K3/32 ,  H01L21/48

CPC classification number: H01L23/34 ,  H01L21/4882 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/4006 ,  H01L23/4093 ,  H01L23/427 ,  H01L23/49822 ,  H01L2023/405 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/13055 ,  H05K1/0206 ,  H05K1/0209 ,  H05K3/284 ,  H05K3/32 ,  H05K5/0034 ,  H05K7/20854 ,  H05K2201/10166 ,  Y10T29/49146 ,  H01L2924/00

Abstract: An electronic device comprises a substrate, at least one electronic chip mounted on and electrically connected to the substrate and being configured as a system control unit for controlling a connected system, a heat removal structure thermally connected to the at least one electronic chip and configured for removing heat generated by the at least one electronic chip upon operation of the electronic device, and an overmolding structure configured for at least partially encapsulating at least the at least one electronic chip and the substrate.

Abstract translation: 电子设备包括基板，安装在基板上并与其电连接的至少一个电子芯片，并且被配置为用于控制连接的系统的系统控制单元，热连接到所述至少一个电子芯片的散热结构， 在电子设备操作时去除由至少一个电子芯片产生的热量，以及被配置用于至少部分地封装至少一个电子芯片和基板的二次模制结构。

公开(公告)号：US12072728B2

公开(公告)日：2024-08-27

申请号：US17975661

申请日：2022-10-28

Applicant: Infineon Technologies AG

Inventor： Wei Wang ,  Lingyun Li ,  Mihail Jefremow ,  Holger Dienst ,  Juergen Schaefer ,  Soenke Ohls

IPC: G06F1/12 ,  G06F1/08

CPC classification number: G06F1/08 ,  G06F1/12

Abstract: A device including at least one processor, and an analog-to-digital (ADC) circuit, wherein the at least one processor is configured to generate an excitation signal and provide the excitation signal to a crystal in a pierce oscillation configuration, wherein after providing the excitation signal, the ADC circuit is configured to obtain as input a signal output from the crystal and convert the signal to a digital output; the at least one processor is configured to compare the digital output of the ADC circuit to a plurality of thresholds and based on the comparisons is further configured to drive the crystal to cause the crystal to operate as a pierce oscillator and to generate a clock signal from at least of one of the comparisons.

公开(公告)号：US11881861B2

公开(公告)日：2024-01-23

申请号：US17584836

申请日：2022-01-26

Applicant: Infineon Technologies AG

Inventor： Sunanda Manjunath ,  Ketan Dewan ,  Juergen Schaefer

IPC: H03K5/1534 ,  H03K5/08 ,  H03K7/08 ,  H03K19/17736 ,  H03K5/05 ,  H03K5/00

CPC classification number: H03K5/1534 ,  H03K5/05 ,  H03K5/086 ,  H03K7/08 ,  H03K19/17744 ,  H03K2005/00136

Abstract: Some examples relate to a system including a pulse modulation (PM) circuit having a PM input and a PM output. The system also includes a load circuit having a load circuit input, and an I/O pad coupling the PM output to the load circuit input. An asymmetry detection circuit has a first asymmetry detection (AD) input coupled to the PM output via a first feedback path, a second AD input coupled to an output node of the I/O pad via a second feedback path, and an AD output coupled to the PM input of the pulse modulation circuit via a control path.

公开(公告)号：US11668763B2

公开(公告)日：2023-06-06

申请号：US17739347

申请日：2022-05-09

Applicant: Infineon Technologies AG

Inventor： Ketan Dewan ,  Rocco Calabro ,  Juergen Schaefer

IPC: G01R31/54 ,  H03M1/12

CPC classification number: G01R31/54 ,  H03M1/124

Abstract: An analog fault detection circuit is disclosed. The analog fault detection circuit comprises an input terminal, an input circuit path coupled to the input terminal at a first end and a first sampling switch coupled to the second end of the input circuit path. The first sampling switch is configured to sample an input path voltage at the second end of the input circuit path to provide a first analog to digital converter (ADC) input voltage. The analog fault detection circuit further comprises a first ADC conversion circuit configured to convert the first ADC input voltage to a first digital ADC output; and a first broken wire detection circuit coupled between the first sampling switch and the first ADC conversion circuit, and configured to adaptively pulldown or pullup the first ADC input voltage, in order to detect a fault associated with a first analog circuit path.

公开(公告)号：US20210248013A1

公开(公告)日：2021-08-12

申请号：US17167546

申请日：2021-02-04

Applicant: Infineon Technologies AG

Inventor： Konrad Walluszik ,  Juergen Schaefer

IPC: G06F9/50 ,  G06F9/54

Abstract: A data processing device is provided. The data processing device includes at least one processor circuit, at least one additional circuit, an accelerator circuit, a first data connection which at least connects the at least one processor circuit to the accelerator circuit and is configured to exchange data between the at least one processor circuit and the accelerator circuit, a second data connection which connects the at least one processor circuit to the at least one additional circuit and is configured to exchange data between the at least one additional circuit and the processor circuit, wherein the first data connection has a higher data rate or a lower latency than the second data connection, and includes an address segment having a first address range, which has at least one first address each for the at least one additional circuit and the accelerator circuit, and a second address range which has at least one second address each for the at least one additional circuit and the accelerator circuit, wherein the data processing device is configured to exchange data using the first data connection when addressing using one of the first addresses, and to exchange data using the second data connection when addressing using one of the second addresses.

公开(公告)号：US20200076655A1

公开(公告)日：2020-03-05

申请号：US16122347

申请日：2018-09-05

Applicant: Infineon Technologies AG

Inventor： Jens Barrenscheen ,  Juergen Schaefer

IPC: H04L25/49

Abstract: A measurement apparatus for providing digital data to a controller, including an Analog-to-Digital Converter (ADC) configured to transform an analog signal into a modulated digital data stream; an event detector configured to generate event indication data based on an event related to the analog signal or the digital data; and a communication interface configured to combine the modulated digital data stream and the event indication data into one or more communication frames, and to transmit the one or more communication frames to the controller.