公开(公告)号：US10886199B1

公开(公告)日：2021-01-05

申请号：US16514115

申请日：2019-07-17

Applicant: Infineon Technologies AG

Inventor： Chau Fatt Chiang ,  Swee Kah Lee ,  Josef Maerz ,  Thomas Stoek ,  Chee Voon Tan

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L23/18

Abstract: A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region which forms part of an electrical connection to the second load terminal.

公开(公告)号：US20180342438A1

公开(公告)日：2018-11-29

申请号：US15605091

申请日：2017-05-25

Applicant: Infineon Technologies AG

Inventor： Liu Chen ,  Teck Sim Lee ,  Jia Yi Wong ,  Wei Han Koo ,  Thomas Stoek ,  Gilles Delarozee

IPC: H01L23/367 ,  H01L23/492 ,  H01L23/495 ,  H01L21/56

Abstract: A semiconductor chip package includes an electrically conducting carrier and a semiconductor chip disposed over the electrically conducting carrier. The semiconductor chip has a first surface facing the electrically conducting carrier and a second surface opposite the first surface. A metal plate has a first surface mechanically connected to the second surface of the semiconductor chip and a second surface opposite the first surface of the metal plate. The metal plate completely overlaps the second surface of the semiconductor chip. The second surface of the metal plate is at least partially exposed at a periphery of the semiconductor chip package.

公开(公告)号：US11769748B2

公开(公告)日：2023-09-26

申请号：US18073090

申请日：2022-12-01

Applicant: Infineon Technologies AG

Inventor： Thomas Stoek ,  Michael Stadler ,  Mohd Hasrul Zulkifli

IPC: H01L23/00 ,  H01L23/495

CPC classification number: H01L24/37 ,  H01L23/49524 ,  H01L24/84 ,  H01L2224/37005 ,  H01L2224/84815

Abstract: A semiconductor device includes a semiconductor die attached to a substrate and a metal clip attached to a side of the semiconductor die facing away from the substrate by a soldered joint. The metal clip has a plurality of slots dimensioned so as to take up at least 10% of a solder paste that reflowed to form the soldered joint. Corresponding methods of production are also described.

公开(公告)号：US11699640B2

公开(公告)日：2023-07-11

申请号：US17353047

申请日：2021-06-21

Applicant: Infineon Technologies AG

Inventor： Thomas Stoek ,  Frank Daeche ,  Chee Voon Tan

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H05K1/18 ,  H05K3/00

CPC classification number: H01L23/49537 ,  H01L21/4825 ,  H01L21/4842 ,  H01L23/49524 ,  H01L24/33 ,  H01L24/83 ,  H01L24/97 ,  H05K1/185 ,  H01L23/49513 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/83203 ,  H01L2224/83385 ,  H01L2224/83815 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0047

Abstract: A power module for PCB embedding includes: a leadframe; a power semiconductor die with a first load terminal and control terminal at a first side of the die and a second load terminal at the opposite side, the second load terminal soldered to the leadframe; a first metal clip soldered to the first load terminal and forming a first terminal of the power module at a first side of the power module; and a second metal clip soldered to the control terminal and forming a second terminal of the power module at the first side of the power module. The leadframe forms a third terminal of the power module at the first side of the power module, or a third metal clip is soldered to the leadframe and forms the third terminal. The power module terminals are coplanar within +/−30 μm at the first side of the power module.

公开(公告)号：US11621204B2

公开(公告)日：2023-04-04

申请号：US17177703

申请日：2021-02-17

Applicant: Infineon Technologies AG

Inventor： Oliver Markus Kreiter ,  Ludwig Busch ,  Angel Enverga ,  Mei Fen Hiew ,  Tian See Hoe ,  Elvis Keli ,  Kean Ming Koe ,  Sanjay Kumar Murugan ,  Michael Niendorf ,  Ivan Nikitin ,  Bernhard Stiller ,  Thomas Stoek ,  Ke Yan Tean

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor module includes: a dual-gauge leadframe having thicker and thinner parts, part of the thinner part forming a high voltage lead; a semiconductor die attached to the thicker part; and a molding compound (MC) encapsulating the die. The thicker leadframe part is disposed at a bottom side of the MC. A side face of the MC has a stepped region between the high voltage lead and thicker leadframe part. A first generally vertical part of the stepped region extends from the high voltage lead to the generally horizontal part, a generally horizontal part of the stepped region extends to the second generally vertical part, and a second generally vertical part of the stepped region extends to the bottom side of the MC. A linear dimension of the generally horizontal part as measured from the first generally vertical part to the second generally vertical part is at least 4.5 mm.

公开(公告)号：US11545459B2

公开(公告)日：2023-01-03

申请号：US17155241

申请日：2021-01-22

Applicant: Infineon Technologies AG

Inventor： Thomas Stoek ,  Michael Stadler ,  Mohd Hasrul Zulkifli

IPC: H01L23/00 ,  H01L23/495

Abstract: A semiconductor device includes a semiconductor die attached to a substrate and a metal clip attached to a side of the semiconductor die facing away from the substrate by a soldered joint. The metal clip has a plurality of slots dimensioned so as to take up at least 10% of a solder paste reflowed to form the soldered joint. Corresponding methods of production are also described.

公开(公告)号：US20220406692A1

公开(公告)日：2022-12-22

申请号：US17353047

申请日：2021-06-21

Applicant: Infineon Technologies AG

Inventor： Thomas Stoek ,  Frank Daeche ,  Chee Voon Tan

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H05K1/18

Abstract: A power module for PCB embedding includes: a leadframe; a power semiconductor die with a first load terminal and control terminal at a first side of the die and a second load terminal at the opposite side, the second load terminal soldered to the leadframe; a first metal clip soldered to the first load terminal and forming a first terminal of the power module at a first side of the power module; and a second metal clip soldered to the control terminal and forming a second terminal of the power module at the first side of the power module. The leadframe forms a third terminal of the power module at the first side of the power module, or a third metal clip is soldered to the leadframe and forms the third terminal. The power module terminals are coplanar within +/−30 μm at the first side of the power module.

公开(公告)号：US11183445B2

公开(公告)日：2021-11-23

申请号：US16776026

申请日：2020-01-29

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Frank Daeche ,  Daniel Schleisser ,  Thomas Stoek

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/31 ,  H01L25/075 ,  H01L25/07 ,  H01L25/04 ,  H01L25/11 ,  H01L25/065

Abstract: A semiconductor arrangement comprises a leadframe comprising at least a first and a second carrier, the first and second carriers being arranged laterally besides each other, at least a first and a second semiconductor die, the first semiconductor die being arranged on and electrically coupled to the first carrier and the second semiconductor die being arranged on and electrically coupled to the second carrier, and an interconnection configured to mechanically fix the first carrier to the second carrier and to electrically insulate the first carrier from the second carrier, wherein the first and second semiconductor dies are at least partially exposed to the outside.

公开(公告)号：US10971436B2

公开(公告)日：2021-04-06

申请号：US16440037

申请日：2019-06-13

Applicant: Infineon Technologies AG

Inventor： Thomas Stoek ,  Chii Shang Hong ,  Chiew Li Tai ,  Edmund Sales Cabatbat

IPC: H01L23/495 ,  H01L23/00

Abstract: An example multi-branch terminal for an integrated circuit (IC) package is described herein. An example multi-branch terminal of an integrated circuit (IC), may include a first branch that may include an active bonding with a chip of the IC, wherein the active bonding may include a wire bonded to the chip of the IC; and a second branch that may include a passive bonding with the chip of the IC, wherein the passive bonding may include a capacitor bonded to the second branch and a first terminal of the IC.

公开(公告)号：US20210020550A1

公开(公告)日：2021-01-21

申请号：US16924851

申请日：2020-07-09

Applicant: Infineon Technologies AG

Inventor： Chau Fatt Chiang ,  Swee Kah Lee ,  Josef Maerz ,  Thomas Stoek ,  Chee Voon Tan

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region that is electrically conductive.