公开(公告)号：US20160093377A1

公开(公告)日：2016-03-31

申请号：US14498480

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Mani Prakash ,  Edward L. Payton ,  John K. Grooms ,  Dimitrios Ziakas ,  Mohammed Arafa ,  Raj K. Ramanujan ,  Dong Wang

IPC: G11C14/00 ,  G11C7/10 ,  G11C11/406

CPC classification number: G11C14/0018 ,  G11C5/04 ,  G11C7/1072 ,  G11C11/40615

Abstract: Memory modules, controllers, and electronic devices comprising memory modules are described. In one embodiment, a memory module comprises a nonvolatile memory and an interface to a volatile memory bus, at least one input power rail to receive power from a host platform, and a controller comprising logic, at least partially including hardware logic, to convert the power from the input power rail from an input voltage to at least one output voltage, different from the input voltage. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了包括存储器模块的存储器模块，控制器和电子设备。 在一个实施例中，存储器模块包括非易失性存储器和到易失性存储器总线的接口，至少一个用于从主机平台接收电力的输入电源轨，以及控制器，其包括至少部分地包括硬件逻辑的逻辑，以将 从输入电源轨从输入电压到不同于输入电压的至少一个输出电压的电力。 还公开并要求保护其他实施例。

公开(公告)号：US20220004468A1

公开(公告)日：2022-01-06

申请号：US17479267

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Thomas Willhalm ,  Francesc Guim Bernat ,  Karthik Kumar ,  Rita Gupta ,  Mark Schmisseur ,  Dimitrios Ziakas

IPC: G06F11/20 ,  G06F11/14 ,  G06F9/50 ,  G06F9/445 ,  G06F12/14

Abstract: An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller to allocate a first secure portion of a pooled memory to a first instantiation of an application on a first node, and circuitry coupled to the one or more substrates and the controller, the circuitry to provide a failover interface for a second instantiation of the application on a second node to access the first secure portion of the pooled memory in the event of a failure of the first node. Other embodiments are disclosed and claimed.

公开(公告)号：US20210349512A1

公开(公告)日：2021-11-11

申请号：US17443374

申请日：2021-07-26

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Alexander Bachmutsky ,  Dimitrios Ziakas ,  Rita D. Gupta

IPC: G06F1/26

Abstract: In one embodiment, an apparatus includes an interface to couple a plurality of devices of a system, the interface to enable communication according to a Compute Express Link (CXL) protocol, and a power management circuit coupled to the interface. The power management circuit may: receive, from a first device of the plurality of devices, a request according to the CXL protocol for updated power credits; identify at least one other device of the plurality of devices to provide at least some of the updated power credits; and communicate with the first device and the at least one other device to enable the first device to increase power consumption according to the at least some of the updated power credits. Other embodiments are described and claimed.

公开(公告)号：US11036642B2

公开(公告)日：2021-06-15

申请号：US16396576

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Dimitrios Ziakas ,  Mark A. Schmisseur ,  Kshitij A. Doshi ,  Kimberly A. Malone

IPC: G06F9/50 ,  G06F12/0888 ,  G06F12/1027 ,  G06N3/04 ,  G06F12/06

Abstract: A semiconductor chip is described. The semiconductor chip includes memory address decoder logic circuitry comprising different memory address bit manipulation paths to respectively impose different memory interleaving schemes for memory accesses directed to artificial intelligence information in a memory and non artificial intelligence information in the memory. The artificial intelligence information is to be processed with artificial intelligence logic circuitry disposed locally to the memory.

公开(公告)号：US10719443B2

公开(公告)日：2020-07-21

申请号：US16363992

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Raj K. Ramanujan ,  Rajat Agarwal ,  Kai Cheng ,  Taarinya Polepeddi ,  Camille C. Raad ,  David J. Zimmerman ,  Muthukumar P. Swaminathan ,  Dimitrios Ziakas ,  Mohan J. Kumar ,  Bassam N. Coury ,  Glenn J. Hinton

IPC: G11C11/406 ,  G06F12/0811 ,  G06F12/0895 ,  G06F12/0897 ,  G11C14/00

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”

公开(公告)号：US20190034383A1

公开(公告)日：2019-01-31

申请号：US15859369

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Mark Schmisseur ,  Dimitrios Ziakas ,  Murugasamy K. Nachimuthu

IPC: G06F15/173 ,  G06F13/16 ,  G06F12/02 ,  G06F12/14

Abstract: Technologies for providing remote access to a shared memory pool include a memory sled. The memory sled includes a memory pool having one or more byte-addressable memory devices and a memory pool controller coupled to the memory pool. The memory pool controller is to produce, for each of a plurality of compute sleds, address space data indicative of addresses of byte-addressable memory in the memory pool accessible to the compute sled, and corresponding permissions associated with the addresses. The memory pool controller is also to provide the address space data to each corresponding compute sled and receive, from a requesting compute sled of the plurality of compute sleds, a memory access request. The memory access request includes an address from the address space data to be accessed. The memory pool controller is also to perform, in response to receiving the memory access request, a memory access operation on the memory pool. Other embodiments are also described and claimed.

公开(公告)号：US20180007791A1

公开(公告)日：2018-01-04

申请号：US15702709

申请日：2017-09-12

Applicant: Intel Corporation

Inventor： Mani Prakash ,  Thomas T. Holden ,  Jeffory L. Smalley ,  Ram S. Viswanath ,  Bassam N. Coury ,  Dimitrios Ziakas ,  Chong J. Zhao ,  Jonathan W. Thibado ,  Gregorio R. Murtagian ,  Kuang C. Liu ,  Rajasekaran Swaminathan ,  Zhichao Zhang ,  John M. Lynch ,  David J. Llapitan ,  Sanka Ganesan ,  Xiang Li ,  George Vergis

IPC: H05K1/18 ,  H01L23/00 ,  H01L23/498 ,  H01R12/71 ,  H01R12/79

CPC classification number: H05K1/181 ,  H01L23/00 ,  H01L23/498 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01R12/712 ,  H01R12/79 ,  H05K2201/10159 ,  H05K2201/10325 ,  Y02P70/611

Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.