公开(公告)号：US20220199515A1

公开(公告)日：2022-06-23

申请号：US17690964

申请日：2022-03-09

申请人： Intel Corporation

发明人： Srinivas V. PIETAMBARAM ,  Jung Kyu HAN ,  Ali LEHAF ,  Steve CHO ,  Thomas HEATON ,  Hiroki TANAKA ,  Kristof DARMAWIKARTA ,  Robert Alan MAY ,  Sri Ranga Sai BOYAPATI

IPC分类号： H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

摘要： A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.

公开(公告)号：US20210134727A1

公开(公告)日：2021-05-06

申请号：US16473598

申请日：2017-03-30

申请人： INTEL CORPORATION

发明人： Robert A. May ,  Sri Ranga Sai BOYAPATI ,  Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Srinivas V. PIETAMBARAM ,  Frank TRUONG ,  Praneeth AKKINEPALLY ,  Andrew J. BROWN ,  Lauren A. LINK ,  Prithwish CHATTERJEE

IPC分类号： H01L23/538 ,  H01L21/48

摘要： An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.

公开(公告)号：US20190019691A1

公开(公告)日：2019-01-17

申请号：US16071826

申请日：2016-02-26

申请人： INTEL CORPORATION

发明人： Srinivas V. PIETAMBARAM ,  Rahul N. MANEPALLI

IPC分类号： H01L21/48 ,  H01L21/683 ,  H01L23/498

摘要： Embodiments herein may relate to providing, on a pad coupled with a carrier panel, a sacrificial element. Embodiments may further relate to providing, on the pad, a mold compound, wherein the mold compound is at least partially adjacent to the sacrificial element. Embodiments may further relate to removing, subsequent to the providing of the mold compound, the sacrificial element to form a via in the mold compound to at least partially expose the pad. Other embodiments may be described and/or claimed.

公开(公告)号：US20240321656A1

公开(公告)日：2024-09-26

申请号：US18126134

申请日：2023-03-24

申请人： Intel Corporation

发明人： Gang DUAN ,  Aaron GARELICK ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM

IPC分类号： H01L23/15 ,  H01L23/498

CPC分类号： H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838

摘要： Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core, where the core comprises glass, and an insert in the core. In an embodiment, the insert is a different material than the core. In an embodiment, a first layer is over the core and a second layer is under the core. In an embodiment, a notch is provided through the first layer, the core, and the second layer. In an embodiment, the notch passes through the insert in the core.

公开(公告)号：US20240312888A1

公开(公告)日：2024-09-19

申请号：US18121264

申请日：2023-03-14

申请人： Intel Corporation

发明人： Sashi S. KANDANUR ,  Srinivas V. PIETAMBARAM ,  Darko GRUJICIC ,  Brandon C. MARIN ,  Suddhasattwa NAD ,  Benjamin DUONG ,  Gang DUAN ,  Mohammad Mamunur RAHMAN ,  Numair AHMED

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/15

CPC分类号： H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49838

摘要： Embodiments herein relate to systems, apparatuses, techniques and/or processes for creating a substrate out of a plurality of layers of glass, where the substrate includes one or more vias that extend through each of the plurality of layers of glass. In embodiments, a high aspect ratio via may be constructed through the substrate by electrically coupling the individual vias. Other embodiments may be described and/or claimed.

公开(公告)号：US20240105580A1

公开(公告)日：2024-03-28

申请号：US17953213

申请日：2022-09-26

申请人： Intel Corporation

发明人： Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Kyle MCELHINNY ,  Hiroki TANAKA

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L23/15

CPC分类号： H01L23/49866 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/15 ,  H01L23/49838

摘要： Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a core, and a pad over the core. In an embodiment, a shell is around the core, and a surface finish is over the shell. In an embodiment, the electronic package further comprises a solder resist over the pad, where an opening is formed through the solder resist to expose the surface finish.

公开(公告)号：US20240105571A1

公开(公告)日：2024-03-28

申请号：US17954288

申请日：2022-09-27

申请人： Intel Corporation

发明人： Brandon C. MARIN ,  Haobo CHEN ,  Bai NIE ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Jeremy D. ECTON ,  Suddhasattwa NAD

IPC分类号： H01L23/498 ,  H01L21/48

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/49894 ,  H01L23/15

摘要： Embodiments disclosed herein include glass cores and methods of forming glass cores. In an embodiment, a core for an electronic package comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass, In an embodiment, a via opening is provided through the substrate, and a diffusion layer is along the first surface, the second surface, and the via opening.

公开(公告)号：US20240097079A1

公开(公告)日：2024-03-21

申请号：US17949857

申请日：2022-09-21

申请人： Intel Corporation

发明人： Brandon C. MARIN ,  Khaled AHMED ,  Srinivas V. PIETAMBARAM ,  Hiroki TANAKA ,  Paul WEST ,  Kristof DARMAWIKARTA ,  Gang DUAN ,  Jeremy D. ECTON ,  Suddhasattwa NAD

IPC分类号： H01L33/48 ,  H01L25/075 ,  H01L33/00 ,  H01L33/32 ,  H01L33/62

CPC分类号： H01L33/486 ,  H01L25/0753 ,  H01L33/0075 ,  H01L33/32 ,  H01L33/62 ,  H01L2933/0066

摘要： Integrated circuit (IC) packages are disclosed. In some embodiments, an IC package includes a glass substrate, a micro light emitting diode (LED), a semiconductor die, one or more through glass vias (TGVs) and a package substrate. The micro LED is positioned over the glass substrate. The TGVs are integrated into the glass substrate and connect the micro LED to the semiconductor die. The semiconductor die is connected to the package substrate to receive external signals when connected to a motherboard.

公开(公告)号：US20240087971A1

公开(公告)日：2024-03-14

申请号：US17943915

申请日：2022-09-13

申请人： Intel Corporation

发明人： Brandon C. MARIN ,  Gang DUAN ,  Srinivas V. PIETAMBARAM ,  Kristof DARMAWIKARTA ,  Jeremy D. ECTON ,  Suddhasattwa NAD ,  Hiroki TANAKA ,  Pooya TADAYON

IPC分类号： H01L23/15 ,  H01L23/00 ,  H01L23/538

CPC分类号： H01L23/15 ,  H01L23/5381 ,  H01L23/5384 ,  H01L24/16 ,  H01L2224/16225

摘要： Embodiments disclosed herein include interposers and methods of forming interposers. In an embodiment, an interposer comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass. In an embodiment, the interposer further comprises a cavity into the first surface of the substrate, a via through the substrate below the cavity, a first pad in the cavity over the via, and a second pad on the second surface of the substrate under the via.

公开(公告)号：US20240063100A1

公开(公告)日：2024-02-22

申请号：US17889229

申请日：2022-08-16

申请人： Intel Corporation

发明人： Brandon C. MARIN ,  Mohammad Mamunur RAHMAN ,  Jeremy D. ECTON ,  Gang DUAN ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM ,  Kemal AYGÜN ,  Cemil GEYIK

IPC分类号： H01L23/498

CPC分类号： H01L23/49822 ,  H01L23/49838 ,  H01L23/49811

摘要： Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first layer, where the first layer comprises glass, a second layer over the first layer, where the second layer comprises glass, and a third layer over the second layer, where the third layer comprises glass. In an embodiment, a pair of traces are in the second layer, and a first gap is below the pair of traces, where the first gap is in the first layer and the second layer. In an embodiment, a second gap is above the pair of traces, where the second gap is in the second layer and the third layer.