公开(公告)号：US5217917A

公开(公告)日：1993-06-08

申请号：US496280

申请日：1990-03-20

申请人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takemuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

发明人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takemuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

IPC分类号： G11C5/00 ,  G11C5/02 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50

CPC分类号： G11C29/027 ,  G11C11/4074 ,  G11C11/4082 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50012 ,  G11C5/00 ,  G11C5/025 ,  G11C7/1045 ,  G11C11/401 ,  G11C2029/5006 ,  G11C29/78

摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

摘要翻译： 提供了一种半导体存储器件，其包括适于形成具有不同封装规格，不同位结构和不同工作模式的大量类型的DRAM的衬底布置。 结合这些，接合垫被布置在适于不同包装类型的最佳位置处。 还提供了各种布局布置以最小化空间并改善访问时间。 提供了额外的功能，包括改进的输出缓冲器电路，保护电路和测试方法以便于半导体存储器件的操作。

公开(公告)号：US5151772A

公开(公告)日：1992-09-29

申请号：US616705

申请日：1990-11-20

申请人： Yasushi Takahashi ,  Hiromi Matsuura ,  Yoshihisa Koyama ,  Masaya Muranaka ,  Katsutaka Kimura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Hidetoshi Iwai

发明人： Yasushi Takahashi ,  Hiromi Matsuura ,  Yoshihisa Koyama ,  Masaya Muranaka ,  Katsutaka Kimura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Hidetoshi Iwai

IPC分类号： H01L23/522 ,  H01L27/108

CPC分类号： H01L23/5226 ,  H01L27/10805 ,  H01L2924/0002 ,  Y10S257/923

摘要： A semiconductor integrated circuit device is provided which includes a memory cell array located in a generally central area of a semiconductor substrate with peripheral circuits located at both ends of the semiconductor substrate. A wiring layer is also provided which couples the peripheral circuits to one another. This wiring layer is arranged to have a double-layer structure of first and second aluminum layers which are electrically coupled to one another.

摘要翻译： 提供一种半导体集成电路器件，其包括位于半导体衬底的大致中心区域中的存储单元阵列，其具有位于半导体衬底两端的外围电路。 还提供了将外围电路彼此耦合的布线层。 该布线层被布置成具有彼此电耦合的第一和第二铝层的双层结构。

公开(公告)号：US5117393A

公开(公告)日：1992-05-26

申请号：US648885

申请日：1991-01-31

申请人： Kazuyuki Miyazawa ,  Katsuhiro Shimohigashi ,  Jun Etoh ,  Katsutaka Kimura

发明人： Kazuyuki Miyazawa ,  Katsuhiro Shimohigashi ,  Jun Etoh ,  Katsutaka Kimura

IPC分类号： G11C11/401 ,  G01R31/317 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46

CPC分类号： G11C29/46 ,  G01R31/31701

摘要： An address multiplexed dynamic RAM device is provided which is capable of initiating (setting) and terminating (resetting) the test mode in response to the signal level combinations of the row address and column address strobe signals and the write enable signal. The signal level combinations employed correspond to those which are unused in the normal operating mode thereby obviating the need for providing additional external control signal terminals. In addition to writing predetermined data in selected memory cells during the test mode, verficiation of the predetermined data is also implemented during the read phase of the test mode.

公开(公告)号：US08673151B2

公开(公告)日：2014-03-18

申请号：US12490531

申请日：2009-06-24

申请人： Kazuyuki Miyazawa ,  Taketoshi Kanda ,  Yousuke Toujo ,  Aya Ohkubo ,  Osamu Shirota ,  Kenichi Sakuma ,  Masayoshi Wada

发明人： Kazuyuki Miyazawa ,  Taketoshi Kanda ,  Yousuke Toujo ,  Aya Ohkubo ,  Osamu Shirota ,  Kenichi Sakuma ,  Masayoshi Wada

IPC分类号： B01D15/08

CPC分类号： B01J20/28019 ,  B01J20/103 ,  B01J20/28057 ,  B01J20/28078 ,  B01J20/286 ,  B01J20/3204 ,  B01J20/3219 ,  B01J20/3242 ,  B01J20/3259 ,  B01J20/3272 ,  B01J20/3276 ,  B01J2220/54 ,  B01J2220/58 ,  C08J7/12 ,  Y10T428/139 ,  Y10T428/2991

摘要： A method for surface modification of a material by means of introducing the phosphorylcholine group represented by the following formula (1-1) onto the surface of the material by treating a material having amino groups with a chemical compound containing an aldehyde derivative obtained by the oxidative ring-opening reaction of glycerophosphorylcholine. The method of the present invention provides various materials such as medical materials having superior biocompatibility and hydrophilicity.

摘要翻译： 通过将具有氨基的材料与含有通过氧化性的醛衍生物获得的醛衍生物的化合物进行处理，通过将下式（1-1）表示的磷酸胆碱基团引入到材料的表面上来对材料进行表面改性的方法 甘油磷酰胆碱的开环反应。 本发明的方法提供了具有优异的生物相容性和亲水性的医疗材料等各种材料。

公开(公告)号：US20130047891A1

公开(公告)日：2013-02-28

申请号：US13695501

申请日：2010-11-29

申请人： Keigo Takei ,  Kazuyuki Miyazawa

发明人： Keigo Takei ,  Kazuyuki Miyazawa

IPC分类号： B05D1/36 ,  C09D7/12

CPC分类号： C09D5/165 ,  C09D5/1675 ,  C09D183/04 ,  C08K5/544 ,  C08K5/521

摘要： A surface modification method in the present invention is characterized by having a step of applying an application fluid including a compound represented by a general formula of: (in the formula, each of R1, R2, and R3 is independently an alkoxy group with a carbon number of 1 or more and 6 or less and R4 is an alkoxy group with a carbon number of 1 or more and 6 or less or an alkyl group with a carbon number of 1 or more and 6 or less.) and a hydrophilization agent having a functional group capable of producing a silanol group through hydrolysis thereof or a silanol group onto a material having a functional group capable of producing a silanol group through hydrolysis thereof or a silanol group on a surface thereof.

摘要翻译： 本发明的表面改性方法的特征在于，具有涂布包含以下通式表示的化合物的涂布液的工序：（式中，R 1，R 2和R 3各自独立地为碳原子数为1〜 1以上且6以下，R4为碳数为1以上且6以下的烷氧基或碳原子数为1以上6以下的烷基），亲水化剂为 能够通过水解产生硅烷醇基或通过其水解产生硅烷醇基的官能团的材料或其表面上的硅烷醇基的硅烷醇基的官能团。

公开(公告)号：US20120052033A1

公开(公告)日：2012-03-01

申请号：US13258957

申请日：2010-04-02

申请人： Tomonori Toyoda ,  Hideki Shimizu ,  Takumi Kurashima ,  Taizo Fujiyama ,  Kazuyuki Miyazawa

发明人： Tomonori Toyoda ,  Hideki Shimizu ,  Takumi Kurashima ,  Taizo Fujiyama ,  Kazuyuki Miyazawa

IPC分类号： A61K8/81 ,  A61Q5/06 ,  A61K8/894

CPC分类号： C08F220/10 ,  A61K8/34 ,  A61K8/347 ,  A61K8/8158 ,  A61K8/8182 ,  A61K8/891 ,  A61K8/892 ,  A61K8/894 ,  A61K8/898 ,  A61Q5/06 ,  C08F220/18 ,  C08F220/56 ,  C08F2220/286 ,  C08F222/1006

摘要： Disclosed is a hair cosmetic which can achieve fixing of hair (hairstyle) by sticking and also has an excellent arranging ability (also including a restyling ability), and moreover imparts a good sense of use. Specifically disclosed is a hair cosmetic comprising a novel adhesive setting resin which is obtained by combining and polymerizing monomers having a specific structure and has a moderate firmness and a high adhesive force when forming a film and further comprising at least one member selected from a cationic surfactant, a silicone derivative, and a polyhydric alcohol, and an alcohol. Accordingly, a hair cosmetic having both fixing ability and arranging ability, and also imparting an excellent sense of use (smoothness and moistness) is obtained.

摘要翻译： 公开了一种能够通过粘贴实现头发（发型）固定的头发美容品，并且还具有优异的布置能力（还包括再修复能力），并且赋予了良好的使用感。 具体公开了一种包含新型粘合剂固化树脂的毛发化妆品，其通过组合和聚合具有特定结构的单体而获得，并且当形成膜时具有适度的硬度和高的粘合力，并且还包含至少一种选自阳离子表面活性剂 硅氧烷衍生物，多元醇，醇等。 因此，可以获得具有定影能力和排列能力以及赋予极好的使用感（平滑度和湿度）的头发化妆品。

公开(公告)号：US20120045410A1

公开(公告)日：2012-02-23

申请号：US13258677

申请日：2010-03-28

申请人： Tomonori Toyoda ,  Hideki Shimizu ,  Takumi Kurashima ,  Taizo Fujiyama ,  Kazuyuki Miyazawa

发明人： Tomonori Toyoda ,  Hideki Shimizu ,  Takumi Kurashima ,  Taizo Fujiyama ,  Kazuyuki Miyazawa

IPC分类号： A61K8/81 ,  A61Q5/06

CPC分类号： A61Q5/06 ,  A61K8/345 ,  A61K8/60 ,  A61K8/86 ,  C08F220/18 ,  C08F220/20 ,  C08F220/26 ,  C08F220/56 ,  C08F222/1006 ,  C08F2220/286

摘要： A hair cosmetic is provided in which the hair (hair style) can be set due to the adhesiveness thereof and yet which shows an excellent hair-arranging ability (including hair-restyling ability). Specifically disclosed is a hair cosmetic comprising, as a hair-setting resin, an adhesive setting resin which is obtained by combining and polymerizing monomers having specific structures and which shows an appropriate hardness and a high adhesiveness in a step of forming a film. In addition, this hair cosmetic preferably contains at least one component selected from a sugar, a sugar alcohol and an EO/PO derivative. Thus, a hair cosmetic having both a high hair-setting power and a good hair-arranging ability can be obtained.

摘要翻译： 提供了一种头发化妆品，其中可以由于其粘合性而设置头发（发型），但是其显示出优异的头发排列能力（包括头发修复能力）。 具体公开了一种毛发化妆品，其包含作为发型树脂的粘合剂固化树脂，其通过在形成膜的步骤中组合并聚合具有特定结构的单体并且显示出适当的硬度和高粘合性而获得。 此外，该毛发化妆品优选含有选自糖，糖醇和EO / PO衍生物中的至少一种成分。 因此，可以获得具有高发丝功率和良好的头发排列能力的头发化妆品。

公开(公告)号：US20110040053A1

公开(公告)日：2011-02-17

申请号：US12934682

申请日：2009-03-31

申请人： Yukimitsu Suda ,  Kazuyuki Miyazawa

发明人： Yukimitsu Suda ,  Kazuyuki Miyazawa

IPC分类号： C08F120/10 ,  C08G77/395 ,  C07F9/141

CPC分类号： C07F9/091 ,  C08G77/395

摘要： A polysiloxane includes a structural unit in which a functional group represented by a general formula of (in the formula, each of R1, R2, and R3 is independently an alkyl group with a carbon number of 1 or more and 6 or less and m is an integer of 2 or more and 6 or less), an ester bond or an amide bond, a spacer, and a silicon atom are bonded sequentially.

摘要翻译： 聚硅氧烷包括结构单元，其中通式（式中，R 1，R 2和R 3各自独立地为碳数为1以上且6以下的烷基，m为 2以上且6以下的整数），酯键或酰胺键，间隔基和硅原子。

公开(公告)号：US07525334B2

公开(公告)日：2009-04-28

申请号：US11446364

申请日：2006-06-05

申请人： Kazutoshi Shimizume ,  Kazuyuki Miyazawa ,  Shinichi Koga

发明人： Kazutoshi Shimizume ,  Kazuyuki Miyazawa ,  Shinichi Koga

IPC分类号： G01R31/00

CPC分类号： G09G3/006 ,  G09G2300/0842 ,  G09G2310/0248 ,  G09G2310/0275

摘要： A defective pixel examination method includes the steps of applying different voltages to a capacitive element of a first pixel section and a capacitive element of a second pixel section among the plurality of pixel sections; turning on a switch provided between an input electrode of a pixel transistor in the first pixel section and an input electrode of a pixel transistor in the second pixel section and short-circuiting the input electrode of the first pixel transistor and the input electrode of the second pixel transistor; reading a voltage of the capacitive element of the first pixel section and a voltage of the capacitive element of the second pixel section; and detecting defects of a pixel section on the basis of the result of the comparison between the voltage of the capacitive element of the first pixel section and the voltage of the capacitive element of the second pixel section.

摘要翻译： 缺陷像素检查方法包括以下步骤：对多个像素部分中的第一像素部分的电容元件和第二像素部分的电容元件施加不同的电压; 打开设置在第一像素部分中的像素晶体管的输入电极和第二像素部分中的像素晶体管的输入电极之间的开关，并且使第一像素晶体管的输入电极和第二像素晶体管的输入电极短路 像素晶体管; 读取第一像素部分的电容元件的电压和第二像素部分的电容元件的电压; 并且基于第一像素部分的电容元件的电压与第二像素部分的电容元件的电压之间的比较结果来检测像素部分的缺陷。

公开(公告)号：US07499340B2

公开(公告)日：2009-03-03

申请号：US12007336

申请日：2008-01-09

申请人： Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Manabu Tsunozaki ,  Kazuyoshi Oshima ,  Takashi Yamazaki ,  Yuji Sakai ,  Jiro Sawada ,  Yasunori Yamaguchi ,  Tetsurou Matsumoto ,  Shinji Udo ,  Hiroshi Yoshioka ,  Hirokazu Saito ,  Mitsuhiro Takano ,  Makoto Morino ,  Sinichi Miyatake ,  Eiji Miyamoto ,  Yasuhiro Kasama ,  Akira Endo ,  Ryoichi Hori ,  Jun Etoh ,  Masashi Horiguchi ,  Shinichi Ikenaga ,  Atsushi Kumata

发明人： Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Manabu Tsunozaki ,  Kazuyoshi Oshima ,  Takashi Yamazaki ,  Yuji Sakai ,  Jiro Sawada ,  Yasunori Yamaguchi ,  Tetsurou Matsumoto ,  Shinji Udo ,  Hiroshi Yoshioka ,  Hirokazu Saito ,  Mitsuhiro Takano ,  Makoto Morino ,  Sinichi Miyatake ,  Eiji Miyamoto ,  Yasuhiro Kasama ,  Akira Endo ,  Ryoichi Hori ,  Jun Etoh ,  Masashi Horiguchi ,  Shinichi Ikenaga ,  Atsushi Kumata

IPC分类号： G11C7/10

CPC分类号： H01L24/06 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C11/406 ,  G11C29/06 ,  G11C29/12005 ,  G11C29/12015 ,  G11C29/24 ,  G11C29/34 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/70 ,  G11C29/80 ,  G11C29/804 ,  G11C29/832 ,  G11C29/844 ,  G11C2029/2602 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01037 ,  H01L2924/01038 ,  H01L2924/01039 ,  H01L2924/01041 ,  H01L2924/01043 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01054 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/01084 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.

摘要翻译： 形成在半导体芯片上的半导体存储器件包括第一存储器阵列，多个第二存储器阵列，第一电压发生器和第一焊盘。 半导体芯片被分为第一，第二和第三矩形区域，第三矩形区域布置在第一矩形区域和第二矩形区域之间。 第一存储器阵列形成在第一矩形区域中。 第二存储器阵列形成在第二矩形区域中。 电压发生器和第一接合焊盘布置在第三矩形区域中。 第一接合焊盘布置在第一矩形区域和电压发生器之间，并且在电压发生器和第二存储器阵列之间没有布置接合焊盘。