公开(公告)号：US09287406B2

公开(公告)日：2016-03-15

申请号：US14163639

申请日：2014-01-24

Applicant: Macronix International Co., Ltd.

Inventor： Hang-Ting Lue ,  Wei-Chen Chen

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/739 ,  H01L29/423 ,  H01L27/092 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/115

CPC classification number: H01L29/78645 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/092 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/66484 ,  H01L29/7391

Abstract: A dual-mode transistor structure comprises a semiconductor body. The semiconductor body of the device includes a channel region, a p-type terminal region (operable as a source or drain) adjacent a first side of the channel region and an n-type terminal region (operable as a source or drain) adjacent a second side of the channel region. A gate insulator is disposed on a surface of the semiconductor body over the channel region. A gate is disposed on the gate insulator over the channel region. A first assist gate is disposed on a first side of the gate, and a second assist gate is disposed on a second side of the gate. Optionally, a back gate can be included beneath the channel region. Biasing the assist gates can be used to select n-channel or p-channel modes in a single device.

Abstract translation: 双模式晶体管结构包括半导体本体。 器件的半导体本体包括与沟道区的第一侧相邻的沟道区，p型端子区（可操作为源极或漏极）和邻近沟道区的n型端子区域（可用作源极或漏极） 通道区域的第二侧。 栅极绝缘体设置在沟道区域上的半导体本体的表面上。 栅极设置在沟道区域上的栅极绝缘体上。 第一辅助栅极设置在栅极的第一侧上，第二辅助栅极设置在栅极的第二侧上。 可选地，可以在通道区域下面包括后门。 可以使用偏置辅助栅极在单个器件中选择n沟道或p沟道模式。

公开(公告)号：US20160035424A1

公开(公告)日：2016-02-04

申请号：US14446866

申请日：2014-07-30

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuo Pin Chang ,  Chih-Shen Chang ,  Hang-Ting Lue

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C29/024 ,  G11C29/028

Abstract: Control transistors and memory cells within 3D NAND Flash memory arrays may both be created using the same technology, such as charge trapping structures, to simplify the fabrication process. However, the resulting control transistors may initially have higher variability in threshold voltages, when compared to traditional gate-oxide-based control transistors. Provided are exemplary techniques to trim control transistors to provide increased reliability and performance during array operation.

公开(公告)号：US09224474B2

公开(公告)日：2015-12-29

申请号：US14019183

申请日：2013-09-05

Applicant: Macronix International Co., Ltd.

Inventor： Hang-Ting Lue

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  H01L27/115

CPC classification number: G11C16/0475 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  G11C2213/71 ,  H01L27/1157 ,  H01L27/11578

Abstract: A p-channel flash memory device including a 3D NAND array has excellent performance characteristics. Techniques for operating 3D, p-channel NAND arrays include selective programming, selective (bit) erase, and block erase. Selective programming bias arrangements induce band-to-band tunneling current hot electron injection to increase threshold voltages in selected cells. Selective erase biasing arrangements induce −FN hole tunneling to decrease threshold voltages in selected cells. Also, block erase bias arrangements induce −FN hole tunneling in selected blocks of cells.

Abstract translation: 包括3D NAND阵列的p通道闪速存储器件具有优异的性能特性。 用于操作3D，p通道NAND阵列的技术包括选择性编程，选择性（位）擦除和块擦除。 选择性编程偏置布置引起带对隧道电流热电子注入，以增加所选单元格中的阈值电压。 选择性擦除偏置布置引起-FN空穴隧道以降低选定单元中的阈值电压。 此外，块擦除偏置布置在选定的单元块中引起-FN空穴隧穿。

公开(公告)号：US09214471B2

公开(公告)日：2015-12-15

申请号：US14590273

申请日：2015-01-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Shin-Jang Shen ,  Hang-Ting Lue

IPC: G11C16/04 ,  G11C16/06 ,  H01L27/115 ,  G11C16/10 ,  H01L27/102 ,  H01L21/768

CPC classification number: H01L27/11578 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  H01L21/76838 ,  H01L27/1021 ,  H01L27/11582

Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.

公开(公告)号：US09147468B1

公开(公告)日：2015-09-29

申请号：US14471788

申请日：2014-08-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: G11C16/00 ,  G11C11/56 ,  G11C16/10 ,  G11C16/04

CPC classification number: H01L27/11582 ,  G11C11/5671 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/10 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/511 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A vertical channel 3D NAND array is configured for independent double gate operation, establishing two memory sites per frustum of a vertical channel column, and in addition, for multiple-bit-per-cell operation. The memory device can comprise even and odd stacks of conductive strips. Active pillars are arranged between corresponding even and odd stacks of conductive strips. A 3D array includes even memory cells accessible via the active pillars and conductive strips in the even stacks and odd memory cells accessible via the active pillars and conductive strips in the odd stacks of conductive strips. Control circuitry is configured to apply different bias voltages to the even and odd conductive strips, and execute a program operation by which more than one bit of data is stored in both the even memory cell and odd memory cell in a given frustum of a selected active strip.

Abstract translation: 垂直通道3D NAND阵列被配置用于独立的双栅极操作，每个平截头体垂直通道列建立两个存储器位置，另外，对于每个单元的每个单元的操作。 存储器件可以包括偶数和奇数的导电条带。 有源支柱布置在相应的偶数和奇数的导电条之间。 3D阵列包括通过有源支柱可访问的偶数存储器单元和偶数堆叠中的导电条以及可通过有源支柱访问的奇数存储器单元和导电条的奇数叠层中的导电条。 控制电路被配置为向偶数和奇数导电带施加不同的偏置电压，并且执行编程操作，通过该程序操作，在所选活动的给定平截头体中，多于一个位的数据存储在偶数存储单元和奇数存储单元中 跳闸。

公开(公告)号：US08947936B2

公开(公告)日：2015-02-03

申请号：US14166471

申请日：2014-01-28

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Shin-Jang Shen ,  Hang-Ting Lue

IPC: G11C16/04 ,  G11C16/06 ,  H01L27/115 ,  G11C16/10 ,  H01L27/102

CPC classification number: H01L27/11578 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  H01L21/76838 ,  H01L27/1021 ,  H01L27/11582

Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.

Abstract translation: 3D存储器件包括多个由绝缘材料隔开的多条导电材料形式的脊状叠层，布置成可以通过解码电路耦合到读出放大器的串。 在字符串的公共源选择端的字符串选择处，二极管连接到位线结构。 导电材料条具有在脊形叠层的侧面上的侧表面。 布置成可以连接到行解码器的字线的多条导线垂直地延伸在多个脊形叠层上。 存储器元件位于叠层和导电线上的导电条的侧表面之间的交叉点处的界面区域的多层阵列。

公开(公告)号：US08780602B2

公开(公告)日：2014-07-15

申请号：US13913176

申请日：2013-06-07

Applicant: Macronix International Co., Ltd.

Inventor： Hang-Ting Lue

IPC: G11C5/06 ,  G11C5/02

CPC classification number: G11C5/06 ,  G11C5/02 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. The 3D memory is made using only two critical masks for multiple layers.

Abstract translation: 3D存储器件包括多个由绝缘材料隔开的导电材料条带形式的脊形叠层，排列成可通过解码电路耦合到读出放大器的位线。 导电材料条具有在脊形叠层的侧面上的侧表面。 布置成可以连接到行解码器的字线的多条导线垂直地延伸在多个脊形叠层上。 导线符合堆叠的表面。 存储器元件位于叠层和导电线上的导电条的侧表面之间的交叉点处的界面区域的多层阵列。 存储器元件是可编程的，如抗熔丝或电荷捕获结构。 3D存储器仅使用两层用于多层的关键掩模。

公开(公告)号：US20130258784A1

公开(公告)日：2013-10-03

申请号：US13899629

申请日：2013-05-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue ,  Erh-Kun Lai

IPC: H01L29/66 ,  G11C16/04

CPC classification number: H01L29/66833 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/0491 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/792

Abstract: Memory cells comprising thin film transistor, stacked arrays, employing bandgap engineered tunneling layers in a junction free, NAND configuration. The cells comprise a channel region in a semiconductor strip formed on an insulating layer; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer Arrays and methods of operation are described.

Abstract translation: 存储单元包括薄膜晶体管，堆叠阵列，采用无接合的NAND配置的带隙工程隧道层。 单元包括在绝缘层上形成的半导体条中的沟道区; 隧道电介质结构，其设置在所述沟道区上方，所述隧道介电结构包括多层结构，所述多层结构包括至少一层，所述层具有低于与所述沟道区的界面处的空穴 - 设置在隧道介电结构上方的电荷存储层; 设置在电荷存储层上方的绝缘层; 并且设置在绝缘层上方的栅电极描述了阵列和操作方法。

公开(公告)号：US12131772B2

公开(公告)日：2024-10-29

申请号：US17751445

申请日：2022-05-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Shang-Chi Yang ,  Fu-Nian Liang ,  Ken-Hui Chen ,  Chun-Hsiung Hung

IPC: G11C16/00 ,  G11C5/06 ,  G11C11/4072 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C11/4094 ,  G11C5/063 ,  G11C11/4072 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096

Abstract: A three dimension memory device, such as an AND-type memory, includes a memory cell tile, multiple source line switches, multiple first bit line switches to fourth bit line switches. The memory cell tile is divided into a first and a second memory cell sub-tiles. The first bit line switches are respectively coupled to multiple first bit lines of a first part of the first memory cell sub-tile. The second bit line switches are respectively coupled to multiple second bit lines of a second part of the first memory cell sub-tile. The third bit line switches are respectively coupled to multiple third bit lines of a first part of the second memory cell sub-tile. The fourth bit line switches are respectively coupled to multiple fourth bit lines of a second part of the second memory cell sub-tile.

公开(公告)号：US12022654B2

公开(公告)日：2024-06-25

申请号：US17185275

申请日：2021-02-25

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Guan-Ru Lee

IPC: H10B43/10 ,  H10B43/27

CPC classification number: H10B43/27 ,  H10B43/10

Abstract: Provided is a memory device including a substrate, a stack structure, a polysilicon layer, a vertical channel structure, and a charge storage structure. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The polysilicon layer is disposed between the substrate and the stack structure. The vertical channel structure penetrates through the stack structure and the polysilicon layer. The charge storage structure is at least disposed between the vertical channel structure and the plurality of conductive layers.