公开(公告)号：US11107832B2

公开(公告)日：2021-08-31

申请号：US16822696

申请日：2020-03-18

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra V. Mouli ,  Srinivas Pulugurtha

IPC: H01L27/11582 ,  H01L21/02 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/04 ,  H01L29/165 ,  H01L29/66 ,  H01L29/22 ,  H01L21/28

Abstract: Memory devices and electronic systems include an array of vertical memory cells positioned along respective vertical channels to define vertical memory strings. Each of the vertical channels includes a channel material exhibiting an electron mobility of at least about 30 cm2/(V·s) and a room temperature band gap of at least about 1.40 eV (e.g., zinc oxide, silicon carbide, indium phosphide, indium gallium zinc oxide, gallium arsenide, or molybdenum disulfide) and a bottom plug material exhibiting a room temperature band gap of less than about 1.10 eV (e.g., silicon germanium, germanium, or indium gallium arsenide). Methods of fabricating a memory device include forming such a bottom plug material within vertical channels and forming such a channel material electrically coupled to the bottom plug material.

公开(公告)号：US20190067475A1

公开(公告)日：2019-02-28

申请号：US16110217

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Guangyu Huang ,  Chandra V. Mouli ,  Akira Goda ,  Deepak Chandra Pandey ,  Kamal M. Karda

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/24 ,  H01L29/423 ,  H01L29/267 ,  H01L27/11556 ,  H01L29/66 ,  H01L21/02 ,  H01L21/44 ,  H01L21/425

Abstract: A device includes a string driver comprising a channel region between a drain region and a source region. At least one of the channel region, the drain region, and the source region comprises a high band gap material. A gate region is adjacent and spaced from the high band gap material. The string driver is configured for high-voltage operation in association with an array of charge storage devices (e.g., 2D NAND or 3D NAND). Additional devices and systems (e.g., non-volatile memory systems) including the string drivers are disclosed, as are methods of forming the string drivers.

公开(公告)号：US20150037942A1

公开(公告)日：2015-02-05

申请号：US14487921

申请日：2014-09-16

Applicant: Micron Technology, Inc.

Inventor： Chandra V. Mouli ,  Gurtej S. Sandhu

IPC: H01L21/84 ,  H01L29/66 ,  H01L21/3205 ,  H01L29/167 ,  H01L29/16 ,  H01L29/45 ,  H01L29/51 ,  H01L21/265

CPC classification number: H01L21/845 ,  B82Y10/00 ,  G11C11/404 ,  G11C2211/4016 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/32053 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/165 ,  H01L29/167 ,  H01L29/32 ,  H01L29/456 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7841 ,  H01L29/785

Abstract: A memory device and method of making the memory device. Memory device may include a storage transistor at a surface of a substrate. The storage transistor comprises a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first conductivity type. The storage transistor also comprises a gate structure that wraps at least partially around the body portion in at least two spatial planes. A bit line is connected to the first source/drain region and a word line is connected to the gate structure.

Abstract translation: 一种存储装置及其制造方法。 存储器件可以包括在衬底的表面处的存储晶体管。 存储晶体管包括在第一和第二源极/漏极区域之间的主体部分，其中源极/漏极区域是第一导电类型的区域。 存储晶体管还包括栅极结构，其至少部分地围绕至少两个空间平面中的主体部分包围。 位线连接到第一源极/漏极区域，并且字线连接到栅极结构。

公开(公告)号：US20140247674A1

公开(公告)日：2014-09-04

申请号：US13782792

申请日：2013-03-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kamal M. Karda ,  Rajesh N. Gupta ,  Srinivas Pulugurtha ,  Chandra V. Mouli ,  Wolfgang Mueller

IPC: H01L29/78 ,  G11C11/40

CPC classification number: H01L29/7827 ,  G11C11/40 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666

Abstract: Methods, apparatuses, and systems for providing a body connection to a vertical access device. The vertical access device may include a digit line extending along a substrate to a digit line contact pillar, a body connection line extending along the substrate to a body connection line contact pillar, a body region disposed on the body connection line, an electrode disposed on the body region, and a word line extending to form a gate to the body region. A method for operation includes applying a first voltage to the body connection line, and applying a second voltage to the word line to cause a conductive channel to form through the body region. A memory cell array may include a plurality of vertical access devices.

Abstract translation: 用于向垂直存取装置提供身体连接的方法，装置和系统。 垂直进入装置可以包括沿着基板延伸到数字线接触柱的数字线，沿着基板延伸到主体连接线接触柱的主体连接线，设置在主体连接线上的主体区域，设置在主体连接线上的电极 身体区域和延伸以形成到身体区域的门的字线。 一种操作方法包括：将第一电压施加到身体连接线，以及向该字线施加第二电压，以使导电通道通过身体区域形成。 存储单元阵列可以包括多个垂直存取装置。

公开(公告)号：US20210013305A1

公开(公告)日：2021-01-14

申请号：US16509093

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Si-Woo Lee ,  Fatma Arzum Simsek-Ege ,  Deepak Chandra Pandey ,  Chandra V. Mouli ,  John A. Smythe, III

IPC: H01L29/06 ,  H01L27/108 ,  H01L21/762

Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.

公开(公告)号：US20200219899A1

公开(公告)日：2020-07-09

申请号：US16822696

申请日：2020-03-18

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra V. Mouli ,  Srinivas Pulugurtha

IPC: H01L27/11582 ,  H01L21/02 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/04 ,  H01L29/165 ,  H01L29/66 ,  H01L29/22 ,  H01L21/28

Abstract: Memory devices and electronic systems include an array of vertical memory cells positioned along respective vertical channels to define vertical memory strings. Each of the vertical channels includes a channel material exhibiting an electron mobility of at least about 30 cm2/(V·s) and a room temperature band gap of at least about 1.40 eV (e.g., zinc oxide, silicon carbide, indium phosphide, indium gallium zinc oxide, gallium arsenide, or molybdenum disulfide) and a bottom plug material exhibiting a room temperature band gap of less than about 1.10 eV (e.g., silicon germanium, germanium, or indium gallium arsenide). Methods of fabricating a memory device include forming such a bottom plug material within vertical channels and forming such a channel material electrically coupled to the bottom plug material.

公开(公告)号：US09847123B2

公开(公告)日：2017-12-19

申请号：US15423646

申请日：2017-02-03

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  F. Daniel Gealy ,  D. V. Nirmal Ramaswamy ,  Chandra V. Mouli

IPC: G11C11/22 ,  G11C11/56 ,  H01L27/11507 ,  H01L43/02

CPC classification number: G11C11/5657 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  H01L27/11507 ,  H01L28/40 ,  H01L43/02 ,  H01L43/12

Abstract: Multi-bit ferroelectric memory devices and methods of forming the same are provided. One example method of forming a multi-bit ferroelectric memory device can include forming a first ferroelectric material on a first side of a via, removing a material to expose a second side of the via, and forming second ferroelectric material on the second side of the via at a different thickness compared to the first side of the via.

公开(公告)号：US20170148512A1

公开(公告)日：2017-05-25

申请号：US15423646

申请日：2017-02-03

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  F. Daniel Gealy ,  D.V. Nirmal Ramaswamy ,  Chandra V. Mouli

IPC: G11C11/56 ,  H01L43/02 ,  G11C11/22 ,  H01L27/11507

CPC classification number: G11C11/5657 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  H01L27/11507 ,  H01L28/40 ,  H01L43/02 ,  H01L43/12

Abstract: Multi-bit ferroelectric memory devices and methods of forming the same are provided. One example method of forming a multi-bit ferroelectric memory device can include forming a first ferroelectric material on a first side of a via, removing a material to expose a second side of the via, and forming second ferroelectric material on the second side of the via at a different thickness compared to the first side of the via.

公开(公告)号：US20150054063A1

公开(公告)日：2015-02-26

申请号：US14517261

申请日：2014-10-17

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Rajesh N. Gupta ,  Srinivas Pulugurtha ,  Chandra V. Mouli ,  Wolfgang Mueller

IPC: H01L29/78

CPC classification number: H01L29/7827 ,  G11C11/40 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666

Abstract: Methods, apparatuses, and systems for providing a body connection to a vertical access device. The vertical access device may include a digit line extending along a substrate to a digit line contact pillar, a body connection line extending along the substrate to a body connection line contact pillar, a body region disposed on the body connection line, an electrode disposed on the body region, and a word line extending to form a gate to the body region. A method for operation includes applying a first voltage to the body connection line, and applying a second voltage to the word line to cause a conductive channel to form through the body region. A memory cell array may include a plurality of vertical access devices.

Abstract translation: 用于向垂直存取装置提供身体连接的方法，装置和系统。 垂直进入装置可以包括沿着基板延伸到数字线接触柱的数字线，沿着基板延伸到主体连接线接触柱的主体连接线，设置在主体连接线上的主体区域，设置在主体连接线上的电极 身体区域和延伸以形成到身体区域的门的字线。 一种操作方法包括：将第一电压施加到身体连接线，以及向该字线施加第二电压，以使导电通道通过身体区域形成。 存储单元阵列可以包括多个垂直存取装置。

公开(公告)号：US08878271B2

公开(公告)日：2014-11-04

申请号：US13782792

申请日：2013-03-01

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Rajesh N. Gupta ,  Srinivas Pulugurtha ,  Chandra V. Mouli ,  Wolfgang Mueller

IPC: H01L27/108 ,  H01L21/8242 ,  H01L29/78 ,  G11C11/40

CPC classification number: H01L29/7827 ,  G11C11/40 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666

Abstract: Methods, apparatuses, and systems for providing a body connection to a vertical access device. The vertical access device may include a digit line extending along a substrate to a digit line contact pillar, a body connection line extending along the substrate to a body connection line contact pillar, a body region disposed on the body connection line, an electrode disposed on the body region, and a word line extending to form a gate to the body region. A method for operation includes applying a first voltage to the body connection line, and applying a second voltage to the word line to cause a conductive channel to form through the body region. A memory cell array may include a plurality of vertical access devices.

Abstract translation: 用于向垂直存取装置提供身体连接的方法，装置和系统。 垂直进入装置可以包括沿着基板延伸到数字线接触柱的数字线，沿着基板延伸到主体连接线接触柱的主体连接线，设置在主体连接线上的主体区域，设置在主体连接线上的电极 身体区域和延伸以形成到身体区域的门的字线。 一种操作方法包括：将第一电压施加到身体连接线，以及向该字线施加第二电压，以使导电通道通过身体区域形成。 存储单元阵列可以包括多个垂直存取装置。