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公开(公告)号：US20190355426A1
公开(公告)日：2019-11-21
申请号：US15981810
申请日：2018-05-16
Applicant: Micron Technology, Inc.
Inventor： Michael Sheperek , Larry J. Koudele , Steve Kientz
Abstract: A system comprises a memory device comprising a plurality of memory cells; and a processing device coupled to the memory device, the processing device configured to iteratively: determine a set of read results based on reading a subset of memory cells according to read levels maintained within optimization trim data, wherein the optimization trim data initially comprises at least one read level in addition to a target trim; calibrate the set of read levels based on the set of read results; and remove the calibrated read levels from the optimization trim data when the calibrated read levels satisfy a calibration condition.
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公开(公告)号：US20180341552A1
公开(公告)日：2018-11-29
申请号：US15605853
申请日：2017-05-25
Applicant: Micron Technology, Inc.
Inventor： Bruce A. Liikanen , Larry J. Koudele
Abstract: A memory system includes a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: determine background records associated with a programming step, wherein the background records are for representing previous data operations, calculate a trigger measure based on the background records, wherein the trigger measure is for estimating implementation of an error recovery mechanism, and generate an adjusted step based on the trigger measure.
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公开(公告)号：US09384799B2
公开(公告)日：2016-07-05
申请号：US13848703
申请日：2013-03-21
Applicant: Micron Technology, Inc.
Inventor： Larry J. Koudele
CPC classification number: G06F3/0604 , G06F3/0629 , G06F3/0659 , G06F3/0688 , G06F13/4286 , G11C7/1066 , G11C7/1069 , G11C7/1093 , G11C7/1096 , G11C7/16 , G11C7/222 , G11C2207/107 , G11C2207/108
Abstract: Controllers, interfaces, memory devices, methods and systems are disclosed, including a controller configured to interface with a separate memory device and perform an iterative write operation to program a selected memory cell of the memory device to a target state, wherein each iteration of the write operation is configured to successively change a physical state of the selected memory cell. Other controllers, interfaces, memory device, methods and systems are also described, such as those where either a controller or a memory device can throttle a data communication operation, and/or those that utilize customized programming pulses.
Abstract translation: 公开了控制器，接口，存储器件，方法和系统，包括被配置为与单独存储器件接口并执行迭代写入操作以将存储器件的选定存储器单元编程到目标状态的控制器，其中每次迭代 写操作被配置为连续地改变所选存储单元的物理状态。 还描述了其他控制器，接口，存储器件，方法和系统，诸如其中控制器或存储器件可以节制数据通信操作的那些，和/或利用定制编程脉冲的那些。
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公开(公告)号：US20130332793A1
公开(公告)日：2013-12-12
申请号：US13966025
申请日：2013-08-13
Applicant: Micron Technology, Inc.
Inventor： Larry J. Koudele , Robert B. Eisenhuth
IPC: G06F11/07
CPC classification number: H04L7/0331 , G04F10/005 , G06F11/0793 , G11C11/4076 , G11C11/5642 , G11C29/02 , G11C29/12015 , G11C2211/5644 , H03M1/207 , H03M1/54
Abstract: A counter configuration operates in cooperation with a delay configuration such that the counter configuration counts an input interval based on a given clock speed and a given clock interval while the delay configuration provides an enhanced data output that is greater than what would otherwise be provided by the given clock speed. The counter configuration counts responsive to a selected edge in the clock interval. An apparatus in the form of a correction arrangement and an associated method are configured to monitor at least the delay configuration output for detecting a particular time relationship between an endpoint of the input interval and a nearest occurrence of the selected clock edge in the given clock signal that is indicative of at least a potential error in the enhanced data output and determining if the potential error is an actual error for subsequent use in correcting the enhanced data output.
Abstract translation: 计数器配置与延迟配置协同工作，使得计数器配置基于给定的时钟速度和给定的时钟间隔对输入间隔进行计数，而延迟配置提供的增强数据输出大于由 给定时钟速度。 计数器配置响应于时钟间隔中的选定边沿计数。 校正装置和相关方法形式的装置被配置为至少监视延迟配置输出，用于检测输入间隔的端点与给定时钟信号中所选择的时钟沿的最近出现之间的特定时间关系 这表明增强数据输出中至少存在潜在的错误，并且确定潜在误差是否是后续用于校正增强数据输出的实际误差。
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公开(公告)号：US11934666B2
公开(公告)日：2024-03-19
申请号：US17826733
申请日：2022-05-27
Applicant: Micron Technology, Inc.
Inventor： Larry J. Koudele , Bruce A. Liikanen
CPC classification number: G06F3/0619 , G06F3/061 , G06F3/065 , G06F3/0688 , G11C11/5628 , G11C16/3459 , G11C16/3495 , G11C29/021 , G11C29/028 , G11C2207/2254 , G11C2211/5621
Abstract: A memory system includes a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: determine a target profile including distribution targets, wherein each of the distribution targets represent a program-verify target corresponding to a logic value for the memory cells, determine a feedback measure based on implementing a processing level for processing data, and dynamically adjust the program-verify target according to the feedback measure.
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Patent Agency Ranking
公开(公告)号：US11886726B2
公开(公告)日：2024-01-30
申请号：US17542943
申请日：2021-12-06
Applicant: Micron Technology, Inc.
Inventor： Michael Sheperek , Kishore Kumar Muchherla , Mustafa N. Kaynak , Vamsi Pavan Rayaprolu , Bruce A. Liikanen , Peter Feeley , Larry J. Koudele , Shane Nowell , Steven Michael Kientz
CPC classification number: G06F3/064 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G06F12/10 , G11C16/26 , G06F2212/1041 , G11C16/0483
Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initialize a block family associated with a memory device; initialize a timeout associated with the block family; initializing a low temperature and a high temperature using a reference temperature at the memory device; responsive to programming a block residing on the memory device, associate the block with the block family; and responsive to at least one of: detecting expiration of the timeout or determining that a difference between the high temperature and the low temperature is greater than or equal to a specified threshold temperature value, close the block family.
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公开(公告)号：US11727994B2
公开(公告)日：2023-08-15
申请号：US17542694
申请日：2021-12-06
Applicant: Micron Technology, Inc.
Inventor： Michael Sheperek , Kishore Kumar Muchherla , Mustafa N. Kaynak , Vamsi Pavan Rayaprolu , Bruce A. Liikanen , Larry J. Koudele
CPC classification number: G11C16/20 , G11C16/26 , G11C16/30 , G11C16/32 , G11C16/3404 , G11C2207/2254
Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to program a first block in a first die of the memory device and a second block in a second die of the memory device, wherein the first die and the second die are assigned to a die group; and associate the die group with a threshold voltage offset bin.
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公开(公告)号：US11714580B2
公开(公告)日：2023-08-01
申请号：US17865686
申请日：2022-07-15
Applicant: Micron Technology, Inc.
Inventor： Gerald L. Cadloni , Michael Sheperek , Francis Chew , Bruce A. Liikanen , Larry J. Koudele
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0619 , G06F3/0679 , G06F11/1068 , G06F13/1668 , G06F13/4282 , G11C29/52 , G06F3/0614 , G06F12/0238 , G06F2213/0008 , G06F2213/0026 , G06F2213/0028 , G06F2213/0036 , G06F2213/0042
Abstract: Aspects of the present disclosure are directed to performing varying frequency memory sub-system background scans using either or both a timer and an I/O event limit. This can be accomplished by identifying a background scan trigger event from one of multiple possible types of background scan trigger events, such as a timer expiration or reaching an event count limit. In response to the background scan trigger event, a background scan can be initiated on a memory portion. The background scan can produce results, such as CDF-based data. When a metric based on the results exceeds a background scan limit, a refresh relocation can be performed and logged. A metric can be generated based on the CDF-based data, obtained error recovery depth data, or refresh relocation event data. When the metric is above or below corresponding background scan thresholds, a background scan frequency can be adjusted.
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公开(公告)号：US11704217B2
公开(公告)日：2023-07-18
申请号：US17157220
申请日：2021-01-25
Applicant: Micron Technology, Inc.
Inventor： Michael Sheperek , Steven Michael Kientz , Shane Nowell , Mustafa N. Kaynak , Kishore Kumar Muchherla , Larry J. Koudele
CPC classification number: G06F11/3037 , G06F3/064 , G06F3/0619 , G06F3/0679 , G06F11/076 , G06F11/3058
Abstract: A memory system includes a memory device and a processing device, operatively coupled to the memory device. The processing device performs operations comprising: identifying an operating temperature of the memory device; determining that the operating temperature satisfies a temperature condition; modifying a scan frequency parameter for performing a scan operation on representative blocks of a set of blocks in the memory device; and performing the scan operation at a frequency identified by the scan frequency parameter.
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公开(公告)号：US11669398B2
公开(公告)日：2023-06-06
申请号：US17135645
申请日：2020-12-28
Applicant: Micron Technology, Inc.
Inventor： Gerald L. Cadloni , Bruce A. Liikanen , Francis Chew , Larry J. Koudele
CPC classification number: G06F11/1402 , G06F11/1068 , G11C29/52 , G06F2201/805 , G06F2201/82
Abstract: A memory system is disclosed, including a memory component and a processing device configured to decode one or more codewords saved to a memory region of the memory component, detect that a number of bit errors corresponding to the decoding of the codeword exceeds a correction capability of the processing device, and execute an error recovery routine to reduce the number of detected bit errors to within the correction capability. The error recovery routine can include error recovery operations that are sequentially executed either until the number of bit errors is successfully reduced to within the correction capability or until a set of the error recovery operations has been executed. The error recovery operations can be ordered according to one or more factors, including energy used to execute a respective error recovery operation, a duration of the respective operation, and/or a likelihood of success of the respective operation.
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