公开(公告)号：US20180211711A1

公开(公告)日：2018-07-26

申请号：US15935126

申请日：2018-03-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/3445

Abstract: Methods of operating a memory, and apparatus so configured, include applying a first voltage level to a first voltage node connected to a first end of a string of series-connected memory cells, applying a second voltage level to a second voltage node connected to a second end of the string, applying a third voltage level less than the first and second voltage levels to a control gate of a first memory cell of the string while applying the first and second voltage levels to the first and second voltage nodes, and applying a fourth voltage level less than the third voltage level to a control gate of a second memory cell of the string while applying the third voltage level to the control gate of the first memory cell, wherein the first memory cell is closer to the first voltage node than the second memory cell.

公开(公告)号：US10014057B2

公开(公告)日：2018-07-03

申请号：US15615652

申请日：2017-06-06

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/08 ,  G11C5/02 ,  G11C16/04 ,  G11C8/10

CPC classification number: G11C16/08 ,  G11C5/02 ,  G11C5/025 ,  G11C8/10 ,  G11C16/0483

Abstract: Some embodiments include a device having an array of memory cells, a memory control unit at least partially under the array, row decoder circuitry in data communication with the memory control unit, and column decoder circuitry in data communication with the memory control unit. Some embodiments include a device having an array of memory cells, row decoder circuitry and column decoder circuitry. One of the row and column decoder circuitries is within a unit that extends at least partially under the array of memory cells and the other within a unit that is laterally outward of the array of memory cells.

公开(公告)号：US20180122443A1

公开(公告)日：2018-05-03

申请号：US15720960

申请日：2017-09-29

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C8/10 ,  G11C13/00 ,  G11C7/00 ,  G11C7/02 ,  G11C8/12 ,  G11C8/16 ,  G11C8/18 ,  G11C11/408

CPC classification number: G11C8/10 ,  G11C7/00 ,  G11C7/02 ,  G11C8/12 ,  G11C8/16 ,  G11C8/18 ,  G11C11/4087 ,  G11C13/0004 ,  G11C13/003

Abstract: Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. Additional embodiments are described.

公开(公告)号：US20180046375A1

公开(公告)日：2018-02-15

申请号：US15722054

申请日：2017-10-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G06F3/06 ,  G06F12/14 ,  G06F12/06 ,  G06F13/16

CPC classification number: G06F3/0604 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/06 ,  G06F12/0623 ,  G06F12/14 ,  G06F13/1657 ,  G06F13/1694 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/1052 ,  G06F2212/214 ,  G06F2212/2532 ,  Y02D10/14

Abstract: Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation, and performing the subsequent memory access operation.

公开(公告)号：US20170365619A1

公开(公告)日：2017-12-21

申请号：US15693229

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/11582 ,  G11C16/08 ,  H01L27/11556 ,  H01L23/528 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/1157 ,  G11C5/06

CPC classification number: H01L27/11582 ,  G11C5/063 ,  G11C16/08 ,  G11C16/10 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described.

公开(公告)号：US20170287565A1

公开(公告)日：2017-10-05

申请号：US15627212

申请日：2017-06-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa ,  Aaron Yip

IPC: G11C16/28 ,  G11C16/10 ,  G11C16/24 ,  G11C16/04 ,  G11C7/02 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/28 ,  G11C7/02 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3427

Abstract: Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string, and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string.

公开(公告)号：US09711228B1

公开(公告)日：2017-07-18

申请号：US15166613

申请日：2016-05-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G11C16/06 ,  G11C16/14 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/3445

Abstract: Methods of operating a memory include developing first and second voltage levels in first and second semiconductor materials, respectively, forming channel regions for first and second groupings of memory cells, respectively, of a string of series-connected memory cells during an erase operation while applying a third voltage level to control gates of the first grouping of memory cells and applying a fourth voltage level to control gates of the second grouping of memory cells. Apparatus include different groupings of memory cells of a string of series-connected memory cells adjacent respective portions of semiconductor material having a first conductivity type and separated from adjacent portions of semiconductor material having the first conductivity type by portions of semiconductor material having a second conductivity type, and a controller configured to apply respective and different voltage levels to control gates of memory cells of respective different groupings of memory cells during an erase operation.

公开(公告)号：US20160343446A1

公开(公告)日：2016-11-24

申请号：US15227623

申请日：2016-08-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa ,  Aaron Yip

IPC: G11C16/28 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04

CPC classification number: G11C16/28 ,  G11C7/02 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3427

Abstract: Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string.

Abstract translation: 描述了用于降低电容负载的装置和方法。 一种装置包括包括第一和第二虚拟存储器单元的第一存储器串，包括第三和第四伪存储单元的第二存储器串，以及控制单元，被配置为提供第一和第二控制信号，以激活第一和第二虚拟存储单元 并且进一步去激活第二存储器串的第三和第四伪存储单元中的至少一个。

公开(公告)号：US20160267998A1

公开(公告)日：2016-09-15

申请号：US15162238

申请日：2016-05-23

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/32

Abstract: Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential, where each access line is associated with a respective charge storage device of a string of charge storage devices. The electrical potential of a selected one of the access lines is lowered, and a data state of the charge storage device associated with the selected access line is sensed while the electrical potential of the selected access line is being lowered. Additional apparatus and methods are described.

公开(公告)号：US09378823B2

公开(公告)日：2016-06-28

申请号：US14289816

申请日：2014-05-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/3459

Abstract: A memory cell is programmed to at least a first threshold voltage to indicate a particular data value. After waiting for a relaxation time, the memory cell is programmed to at least a second threshold voltage to indicate the particular data value. The second threshold voltage is greater than the first threshold voltage.

Abstract translation: 存储器单元被编程为至少第一阈值电压以指示特定数据值。 在等待放松时间之后，将存储单元编程为至少第二阈值电压以指示特定数据值。 第二阈值电压大于第一阈值电压。