公开(公告)号：US20090097338A1

公开(公告)日：2009-04-16

申请号：US12258285

申请日：2008-10-24

Applicant: Carl Werner ,  Mark Horowitz ,  Pak Chau ,  Scott Best ,  Stefanos Sidiropoulos

Inventor： Carl Werner ,  Mark Horowitz ,  Pak Chau ,  Scott Best ,  Stefanos Sidiropoulos

IPC: G11C7/00

CPC classification number: H04L25/4917 ,  G06F13/1678 ,  G06F13/4068 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/22 ,  G11C8/10 ,  G11C11/56 ,  G11C27/02 ,  G11C2207/108 ,  H04L7/0331 ,  H04L7/0332 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0296 ,  H04L25/0298 ,  H04L25/03006 ,  H04L25/03057 ,  H04L25/08 ,  H04L25/4902

Abstract: A memory device includes a receiver to receive an input data signal and to create an output signal corresponding to the present received data signal and a voltage representative of a signal sampled earlier in time.

Abstract translation: 存储器件包括接收器，用于接收输入数据信号并产生对应于当前接收数据信号的输出信号和代表在时间上较早采样的信号的电压。

公开(公告)号：US20080052440A1

公开(公告)日：2008-02-28

申请号：US11929974

申请日：2007-10-30

Applicant: Mark Horowitz ,  Richard Barth ,  Craig Hampel ,  Alfredo Moncavo ,  Kevin Donnelly ,  Jared Zerbe

Inventor： Mark Horowitz ,  Richard Barth ,  Craig Hampel ,  Alfredo Moncavo ,  Kevin Donnelly ,  Jared Zerbe

IPC: G06F13/14

CPC classification number: G06F13/4291 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1081 ,  G06F13/102 ,  G06F13/1689 ,  G06F13/364 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4234 ,  G06F13/4243 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  G11C19/00 ,  H03K19/00384 ,  H03K19/018585

Abstract: An integrated circuit device includes an output driver, a first register to store a value representative of a drive strength setting of the output driver, wherein the value is determined based on information stored in a supplemental memory device external to the integrated circuit memory device, and a transmitter circuit configurable to receive the value representative of a drive strength setting of the output driver. The output driver is configurable to output data synchronously with respect to an external clock signal.

Abstract translation: 集成电路装置包括输出驱动器，第一寄存器，用于存储代表输出驱动器的驱动强度设置的值，其中该值基于存储在集成电路存储器件外部的补充存储器件中的信息确定，以及 发射机电路可配置为接收代表输出驱动器的驱动强度设置的值。 输出驱动器可配置为相对于外部时钟信号同步输出数据。

公开(公告)号：US20070297520A1

公开(公告)日：2007-12-27

申请号：US11895415

申请日：2007-08-23

Applicant: Andrew Ho ,  Vladimir Stojanovic ,  Fred Chen ,  Elad Alon ,  Mark Horowitz

Inventor： Andrew Ho ,  Vladimir Stojanovic ,  Fred Chen ,  Elad Alon ,  Mark Horowitz

IPC: H04B1/10

CPC classification number: H04L47/10 ,  H04L5/20 ,  H04L25/0276

Abstract: Described are communication systems that convey differential and common-mode signals over the same differential channel. Noise-tolerant communication schemes use low-amplitude common-mode signals that are easily rejected by differential receivers, thus allowing for very high differential data rates. Some embodiments employ the common-mode signals to transmit backchannel signals for adjusting the characteristics of the differential transmitter. Backchannel control signals are effectively conveyed even if the forward channel transmitter is so maladjusted that the received differential data is unrecognizable. Systems in accordance with the above-described embodiments obtain these advantages without additional pins or communications channels, and are compatible with both AC-coupled and DC-coupled communications channels. Data coding schemes and corresponding data recovery circuits eliminate the need for complex, high-speed CDR circuits.

公开(公告)号：US07298807B2

公开(公告)日：2007-11-20

申请号：US10672853

申请日：2003-09-26

Applicant: Jared Zerbe ,  Mark Horowitz ,  Carl Werner

Inventor： Jared Zerbe ,  Mark Horowitz ,  Carl Werner

IPC: H04L7/00

CPC classification number: G11C7/222 ,  G11C7/22 ,  G11C2207/2254 ,  H03L7/07 ,  H03L7/087 ,  H03L7/091 ,  H04L7/033

Abstract: A circuit, apparatus and method for maximizing system margins by adjusting a duty-cycle of a clock signal in a receive circuit to whatever duty-cycle is optimal for the particular incoming serial data, rather than the typical 50% duty-cycle, is provided in embodiments of the present invention. A receive circuit, including duty-cycle-correction logic, is included in a double-data rate communication apparatus having a transmit circuit transmitting serial data having duty-cycle distortion. A receive circuit includes a first and second sampler to obtain data and edge values of an incoming serial data responsive to a data and edge clock, respectively. A duty-cycle-correction logic generates a duty-cycle-correction signal to a duty-cycle clock integrator that adjusts the edge clock signals while maintaining quadrature to the data clocks. In an embodiment of the present invention, a duty-cycle-correction logic includes an evaluator circuit to generate an up or down signal responsive to the data and/or edge values. In a further embodiment of the present invention, an evaluator circuit is coupled to a counter and a DAC to generate a duty-cycle-correction signal to the duty-cycle clock integrator. A digital filter or coding scheme is also used to reduce the likelihood of misinterpreting malevolent incoming serial data for duty-cycle distortion in an embodiment of the present invention.

Abstract translation: 通过将接收电路中的时钟信号的占空比调整到任何占空比来最大化系统裕度的电路，装置和方法对于特定的输入串行数据而言不是典型的50％占空比是最佳的 在本发明的实施例中。 包括占空比校正逻辑的接收电路被包括在具有发送电路的双数据速率通信装置中，该发送电路发送具有占空比失真的串行数据。 接收电路包括第一和第二采样器，用于分别响应于数据和边沿时钟获得输入串行数据的数据和边缘值。 占空比校正逻辑产生占空比校正信号到占空比时钟积分器，该占空比校正信号调整边沿时钟信号同时保持与数据时钟的正交。 在本发明的实施例中，占空比校正逻辑包括响应于数据和/或边缘值产生上升或下降信号的评估器电路。 在本发明的另一实施例中，评估器电路耦合到计数器和DAC，以向占空比时钟积分器产生占空比校正信号。 数字滤波器或编码方案也用于在本发明的一个实施例中减少对恶意输入串行数据进行占空比失真的误解的可能性。

公开(公告)号：US20070143387A1

公开(公告)日：2007-06-21

申请号：US11311971

申请日：2005-12-19

Applicant: Aliazam Abbasfar ,  Amir Amirkhany ,  Vladimir Stojanovic ,  Mark Horowitz

Inventor： Aliazam Abbasfar ,  Amir Amirkhany ,  Vladimir Stojanovic ,  Mark Horowitz

IPC: G06F17/14

CPC classification number: G06J1/00

Abstract: A first device is described. The first device may include a linear transformation circuit to implement multiplication by a matrix D. The linear transformation circuit may have an input to receive a vector having N digital values and an output to output N first output signals, a sign-adjustment circuit to adjust signs of a subset including at least M of the N first output signals in accordance with a set of coefficients H, and a conversion (DAC) circuit coupled to the sign-adjustment circuit. Outputs from the DAC circuit may be summed to produce an output.

Abstract translation: 描述第一设备。 第一装置可以包括线性变换电路以实现矩阵D的乘法。线性变换电路可以具有用于接收具有N个数字值的矢量的输入和用于输出N个第一输出信号的输出，用于调整的符号调整电路 根据一组系数H包括至少N个N个第一输出信号的子集的符号，以及耦合到符号调整电路的转换（DAC）电路。 来自DAC电路的输出可以相加以产生输出。

公开(公告)号：US07209997B2

公开(公告)日：2007-04-24

申请号：US10716596

申请日：2003-11-20

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F13/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G11C5/04 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108

Abstract: A controller device and method for operating same is disclosed. In one particular exemplary embodiment, the controller device may comprise output driver circuitry and input receiver circuitry. The output driver circuitry may output a value, a first operation code, a block size value, and second operation code. The first operation code may represent an instruction to a memory device to store the value in a register in the memory device. The block size value may indicate an amount of read data to be output by the memory device in response to the second operation code. The second operation code may represent an instruction to the memory device to perform a read operation. The input receiver circuitry may sample a first portion of the read data output by the memory device after a read delay following the outputting of the second operation code.

Abstract translation: 公开了一种控制装置及其操作方法。 在一个特定的示例性实施例中，控制器设备可以包括输出驱动器电路和输入接收器电路。 输出驱动器电路可以输出值，第一操作码，块大小值和第二操作码。 第一操作代码可以表示对存储器设备的指令以将该值存储在存储器件中的寄存器中。 块大小值可以指示响应于第二操作码由存储器件输出的读取数据量。 第二操作代码可以表示对存储器件执行读取操作的指令。 输入接收器电路可以在输出第二操作码之后的读取延迟之后，对由存储器件输出的读取数据的第一部分进行采样。

公开(公告)号：US20070058744A1

公开(公告)日：2007-03-15

申请号：US11557101

申请日：2006-11-06

Applicant: Amir Amirkhany ,  Vladimir Stojanovic ,  Elad Alon ,  Jared Zerbe ,  Mark Horowitz

Inventor： Amir Amirkhany ,  Vladimir Stojanovic ,  Elad Alon ,  Jared Zerbe ,  Mark Horowitz

IPC: H04K1/10 ,  H04J11/00 ,  G06F17/14

CPC classification number: G06F17/141 ,  G06J1/005

Abstract: A transform circuit includes a first circuit and a second circuit. The first circuit and the second circuit implement first and second mappings that together generate a pre-defined transform of N digital data symbols. The first circuit maps a set of N digital data symbols from N parallel data streams to N analog data symbols by generating N sets of first weighted sums of the N digital data symbols. Each respective first weighted sum is defined by a respective set of pre-determined first weighting values in a first matrix. The second circuit maps the N analog data symbols to a sequence of N output signals over N time intervals. Each of the N output signals corresponds to a respective second weighted sum of the N analog data symbols. Each respective second weighted sum is defined by a respective set of pre-determined second weighting values in a second matrix.

Abstract translation: 变换电路包括第一电路和第二电路。 第一电路和第二电路实现一起产生N个数字数据符号的预定义变换的第一和第二映射。 第一电路通过产生N个数字数据符号的第一加权和的N组，将来自N个并行数据流的一组N个数字数据符号映射到N个模拟数据符号。 每个相应的第一加权和由第一矩阵中的预定的第一加权值的相应集合来定义。 第二电路在N个时间间隔内将N个模拟数据符号映射到N个输出信号的序列。 N个输出信号中的每一个对应于N个模拟数据符号的相应的第二加权和。 每个相应的第二加权和由第二矩阵中的预定的第二加权值的相应集合来定义。

公开(公告)号：US07093145B2

公开(公告)日：2006-08-15

申请号：US10903572

申请日：2004-07-30

Applicant: Carl Werner ,  Mark Horowitz ,  Pak Chau ,  Scott Best ,  Stefanos Sidiropoulos

Inventor： Carl Werner ,  Mark Horowitz ,  Pak Chau ,  Scott Best ,  Stefanos Sidiropoulos

IPC: G06F1/26 ,  H03K3/00 ,  G01R19/00

CPC classification number: H04L25/4917 ,  G06F13/1678 ,  G06F13/4068 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/22 ,  G11C8/10 ,  G11C11/56 ,  G11C27/02 ,  G11C2207/108 ,  H04L7/0331 ,  H04L7/0332 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0296 ,  H04L25/0298 ,  H04L25/03006 ,  H04L25/03057 ,  H04L25/08 ,  H04L25/4902

Abstract: A current controller for a multi-level current mode driver. The current controller includes a multi-level voltage reference and at least one source calibration signal. A comparator is coupled by a coupling network to the multi-level voltage reference and the at least one source calibration signal. A selected voltage is applied from the multi-level voltage reference and a selected source calibration signal is applied from the at least one source calibration signal to the comparator.

Abstract translation: 用于多电平电流模式驱动器的电流控制器。 电流控制器包括多电平电压基准和至少一个源校准信号。 比较器通过耦合网络耦合到多电平电压基准和至少一个源校准信号。 从多电平参考电压施加所选择的电压，并且将所选择的源校准信号从至少一个源校准信号施加到比较器。

公开(公告)号：US20060158225A1

公开(公告)日：2006-07-20

申请号：US11386984

申请日：2006-03-21

Applicant: Vladimir Stojanovic ,  Andrew Ho ,  Anthony Bessios ,  Fred Chen ,  Elad Alon ,  Mark Horowitz

Inventor： Vladimir Stojanovic ,  Andrew Ho ,  Anthony Bessios ,  Fred Chen ,  Elad Alon ,  Mark Horowitz

IPC: H03K19/094

CPC classification number: H04L25/49 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0416 ,  H04L25/025 ,  H04L25/028 ,  H04L25/0282 ,  H04L25/03019 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/061 ,  H04L25/4917 ,  H04L2025/03363 ,  H04L2025/03802

Abstract: A signaling system having an equalizing transmitter and equalizing receiver. The equalizing transmitter transmits a signal to a receive circuit. A first sampling circuit within the equalizing receiver samples the signal to determine whether the signal exceeds a first threshold, and a second sampling circuit within the equalizing receiver samples the signal to determine whether the signal exceeds a second threshold. A drive strength of the equalizing transmitter and a drive strength of an equalizing signal driver within the equalizer are adjusted based, at least in part, on whether the first signal exceeds the first and second thresholds.

公开(公告)号：US20060059299A1

公开(公告)日：2006-03-16

申请号：US11270251

申请日：2005-11-08

Applicant: Richard Barth ,  Ely Tsern ,  Mark Horowitz ,  Donald Stark ,  Craig Hampel ,  Frederick Ware ,  John Dillon ,  Nancy Dillon

Inventor： Richard Barth ,  Ely Tsern ,  Mark Horowitz ,  Donald Stark ,  Craig Hampel ,  Frederick Ware ,  John Dillon ,  Nancy Dillon

IPC: G06F12/00

CPC classification number: G11C7/1006 ,  G06F13/1615 ,  G11C7/10 ,  G11C7/1039 ,  G11C8/12 ,  G11C11/4076

Abstract: A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.