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公开(公告)号：US20090051401A1
公开(公告)日：2009-02-26
申请号：US12035235
申请日：2008-02-21
IPC分类号： H03L5/00
CPC分类号： H03H7/0153 , H03H1/02 , H03H2210/021 , H03H2210/043
摘要： A calibration circuit for calibrating an adjustable capacitance of a circuit having a time constant depending on the adjustable capacitance, the calibration circuit generating a calibration signal for calibrating the capacitance and including a calibration loop, suitable to carry out a calibration cycle in several sequential steps. The calibration circuit includes a controllable capacitance for receiving a control signal and including an array of switched capacitors selectively activated by the control signal to connect to a first common node that conducts a voltage value depending on the total capacitance value of the activated capacitors; an assessment unit for comparing this voltage value with a reference voltage to output a logic signal that can transition between first and second logic levels; a control and timing unit to receive the logic signal and change the control signal to carry out a subsequent calibration step that is provided at the end of the integration interval during a comparison interval of a preset duration, which allows a transition of the logic signal to occur prior to the beginning of the consecutive calibration step.
摘要翻译： 一种用于校准具有取决于可调电容的时间常数的电路的可调电容的校准电路，所述校准电路产生用于校准电容的校准信号，并且包括适于在几个连续步骤中执行校准循环的校准环路。 校准电路包括用于接收控制信号并包括由控制信号选择性激活的开关电容阵列的可控电容，以连接到第一公共节点，该第一公共节点根据所激活的电容器的总电容值传导电压值; 评估单元，用于将该电压值与参考电压进行比较，以输出可在第一和第二逻辑电平之间转换的逻辑信号; 控制和定时单元，用于接收逻辑信号并改变控制信号，以执行在预设持续时间的比较间隔期间在积分间隔结束时提供的随后的校准步骤，这允许将逻辑信号转换为 在连续校准步骤开始之前发生。
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公开(公告)号：US5712777A
公开(公告)日：1998-01-27
申请号：US414277
申请日：1995-03-31
IPC分类号： H01L27/04 , H01L21/822 , H02M3/07
CPC分类号： H02M3/07 , H02M2001/0045
摘要： A voltage multiplier includes a first charge transfer capacitor designed to take and transfer electrical charges from the input terminal to the output terminal, a second capacitor for charge storage connected between the output terminal and ground and an output voltage stabilization circuit. The output voltage stabilization circuit includes an integrator designed to generate a continuous voltage corresponding to the difference between a reference voltage and the output voltage of the voltage multiplier. The continuous voltage is applied to one terminal of said charge transfer capacitor so that the potential at the other terminal of the capacitor changes proportionally to the output voltage of the voltage multiplier.
摘要翻译： 电压倍增器包括：第一电荷转移电容器，被设计用于从输入端子到输出端子接收和传送电荷;第二电容器，用于连接在输出端子和地之间的电荷存储器;以及输出电压稳定电路。 输出电压稳定电路包括积分器，其被设计为产生对应于参考电压和电压倍增器的输出电压之间的差的连续电压。 将连续电压施加到所述电荷转移电容器的一个端子，使得电容器另一端的电位与电压倍增器的输出电压成比例地变化。
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23.发明授权Circuit for PCM conversion of an analog signal, with improvement in gain-tracking 失效模拟信号的PCM转换电路，具有增益跟踪的改进
公开(公告)号：US5287106A
公开(公告)日：1994-02-15
申请号：US187507
申请日：1988-04-28
CPC分类号： H03M1/0604 , H03M1/12
摘要： The circuit includes a filter to which an analog signal is applied, a quantizer driven by the filter, a sampler at a desired frequency driven by the quantizer and a PCM encoder driven by the sampler. The quantizer generates a quantize signal according to the received analog signal and further generates a difference signal according to the difference between a quantized signal and the analog signal. A feedback circuit feeds back the difference signal from the quantizer to a stage of the filter so that the overall transfer function from the input of the feedback circuit to the output of the filter is equivalent to a low pass filtering.
摘要翻译： 电路包括施加模拟信号的滤波器，由滤波器驱动的量化器，由量化器驱动的期望频率的采样器和由采样器驱动的PCM编码器。 量化器根据接收到的模拟信号生成量化信号，并根据量化信号和模拟信号之间的差产生差分信号。 反馈电路将差分信号从量化器反馈到滤波器的级，使得从反馈电路的输入到滤波器的输出的整体传递函数等效于低通滤波。
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公开(公告)号：US4965468A
公开(公告)日：1990-10-23
申请号：US417588
申请日：1989-10-05
CPC分类号： H03K3/356034 , H03F3/45192 , H03F3/45475 , H03F3/45659 , H03F3/45977 , H03F2203/45406 , H03F2203/45644 , H03F2203/45651 , H03F2203/45652 , H03F2203/45728
摘要： A high resolution, fully differential, CMOS comparator advantageously employs a single high-gain, "folded cascode", fully differential operational amplifier and an output latch circuit and the output common mode control of the high-gain amplifier is implemented without requiring the use of a conventional control circuit, thus improving layout economy. The common mode control is performed by providing the latch with a differential input stage through which a common mode feedback network is realized which acts upon a pair of output transistors of the operational amplifier for effectively controlling the output common mode thereof. The comparator has a simplified layout and is remarkably faster because it has no additional capacitances loading the outputs of the amplifier.
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公开(公告)号：US4888500A
公开(公告)日：1989-12-19
申请号：US171954
申请日：1988-03-23
IPC分类号： H01L21/82 , H01L21/8249 , H01L27/06 , H03K19/00 , H03K19/0175 , H03K19/0185
CPC分类号： H03K19/018521 , H03K19/0013
摘要： The TTL-compatible cell comprising two cascade coupled CMOS inverters is associated with an input pin of the integrated circuit to make it suitable to receive signals in TTL logic, as well as with a power-down pin, and is characterized in that said input (10) of the CMOS integrated circuit is connected to the input of the first of said two inverters (12, 14) through a first and a second respectively P-channel and N-channel MOS transistor in parallel (28, 30), the first controlled by the power-down pin (31), the second by an inverter (32) driven by said power-down pin, so as to be both off when the power-down signal is at logical 1 and active when the power-down signal is at logical 0. Between the input of the first inverter and the ground a further MOS transistor (34) is connected the gate whereof is controlled so that said further MOS transistor is active when the power-down signal is at logical 1 and is off when the power-down signal is at logical 0.
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26.发明授权Buffer circuit with differential structure for measurement of capacitive charges 失效具有差分结构的缓冲电路，用于测量电容性电荷
公开(公告)号：US4609877A
公开(公告)日：1986-09-02
申请号：US795834
申请日：1985-11-07
CPC分类号： G01R29/24
摘要： In a buffer with an operational amplifier having two inputs and two outputs and two feedback capacitances are inserted two other capacitances which in the measurement stage are switched in parallel to the feedback ones with opposite sign in such a manner as to cancel out the effects on the output voltage signal.
摘要翻译： 在具有两个输入和两个输出的运算放大器和两个反馈电容的缓冲器中插入两个其他电容，其中测量级与具有相反符号的反馈开关平行地切换，以抵消对 输出电压信号。
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27.发明授权Current steering digital-analog converter particularly insensitive to packaging stresses 有权电流转向数模转换器特别对包装应力不敏感公开(公告)号：US07675449B2
公开(公告)日：2010-03-09
申请号：US12172692
申请日：2008-07-14
IPC分类号： H03M1/66
CPC分类号： H03M1/0648 , H03M1/687 , H03M1/747
摘要： A current steering digital-analog converter for converting a digital code into an analog signal, the converter including a substrate of semiconductor material, an array of current generators integrated in the substrate, a common summation node and switches controllable on the basis of the digital code for connecting and disconnecting the current generators to and from the common summation node. The current generators are adapted to provide the common summation node with currents having a multiple value according to a power of two compared to a unit current value provided to the summation node by a current generator of the array of generators. The current generator is divided into a base number of modular current generation elements in parallel to one another at least equal to two.
摘要翻译： 一种用于将数字代码转换为模拟信号的电流转向数模转换器，所述转换器包括半导体材料的衬底，集成在衬底中的电流发生器的阵列，公共求和节点和基于数字代码可控的开关 用于将当前发生器连接到和从公共求和节点断开连接。 电流发生器适于根据与发电机阵列的电流发生器提供给求和节点的单位电流值相比的功率，为公共求和节点提供具有多个值的电流。 电流发生器被分成基本数量的模块化电流产生元件，彼此平行至少等于2。
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公开(公告)号：US20050195010A1
公开(公告)日：2005-09-08
申请号：US11055564
申请日：2005-02-09
CPC分类号： H03H11/26 , H03K5/04 , H03K5/133 , H03K2005/00071 , H03K2005/00123 , H03K2005/00143 , H03K2005/00156 , H03K2005/00195
摘要： A time delay logic comprises a first stage with an inverter, a capacitor connected to the input terminal of the inverter, a constant current generator and an electronic switch controlled by an input pulse. The capacitor begins to charge at a predetermined edge of the input pulse and brings the input terminal of the inverter from a first voltage (ground) to the switching threshold voltage of the inverter, so that on the output terminal of the inverter there is obtained a pulse having an edge that, as referred to the predetermined edge of the input pulse, has a delay time that depends on the inverter threshold. The circuit comprises a second stage, coupled with the first, that is a dual circuit of the circuit of the first stage and has an inverter equal to the one of the first stage.
摘要翻译： 时间延迟逻辑包括具有逆变器的第一级，连接到逆变器的输入端的电容器，恒定电流发生器和由输入脉冲控制的电子开关。 电容器开始在输入脉冲的预定边沿充电，并将逆变器的输入端从第一电压（接地）转换到逆变器的开关阈值电压，从而在逆变器的输出端上获得 具有如参照输入脉冲的预定边缘具有取决于反相器阈值的延迟时间的边缘的脉冲。 电路包括与第一级耦合的第二级，即第一级的电路的双电路，并且具有等于第一级中的一级的反相器。
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29.发明授权High-speed, high-resolution and low-consumption analog/digital converter with single-ended input 有权具有单端输入的高速，高分辨率和低功耗模拟/数字转换器公开(公告)号：US06897801B2
公开(公告)日：2005-05-24
申请号：US10483790
申请日：2002-06-13
CPC分类号： H03M1/0682 , H03M1/468 , H03M1/804
摘要： An A/D converter having capacitors of a first array of sampling capacitors weighted in binary code connected between a first common circuit node and an input terminal to be charged to an input voltage with respect to a ground of a signal to be converted, and in accordance with SAR technique are then selectively connected with two differential reference terminals, and at the same time capacitors of a second array equal to the first and all connected to a second node are selectively connected to ground and the lower differential voltage terminal. The two nodes are connected to the respective inputs of a comparator. A logic unit controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator.
摘要翻译： 一种A / D转换器，具有电容器，其具有以二进制代码加权的采样电容器的第一阵列阵列，连接在第一公共电路节点和待充电的输入端子之间，所述第一公共电路节点和输入端子相对于要转换的信号的接地为输入电压， 然后根据SAR技术选择性地与两个差分参考端子连接，并且同时等效于第一和所有连接到第二节点的第二阵列的电容器选择性地连接到地和下差分电压端子。 两个节点连接到比较器的相应输入端。 逻辑单元根据预定的定时程序和作为比较器的输出的函数来控制两个阵列的电容器的连接。
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公开(公告)号：US5763907A
公开(公告)日：1998-06-09
申请号：US763937
申请日：1996-12-12
CPC分类号： H01L27/0207
摘要： A cell library for the design of integrated circuits, for example using CMOS technology, includes cells which define circuit modules in rectangular areas having an identical side. Two traces are provided which extend at right-angles to the identical side and which define strips for connection to the supply, at least one of which is in contact with the source regions of MOS transistors of a CMOS pair. In order to permit the design of integrated circuits in which the analog parts are insensitive to the noise induced in the substrate by the digital parts and in which it is possible to reduce the current absorption of the digital parts in stand-by mode, the cell library also provides a group of cells in which there is provided at least one additional trace which defines an additional strip for connection to the outside and which is in contact with the body regions of the MOS transistors of the CMOS pair.
摘要翻译： 用于设计集成电路的单元库，例如使用CMOS技术，包括在具有相同侧面的矩形区域中定义电路模块的单元。 提供了两条迹线，它们以直角延伸到同一侧，并且限定了用于连接到电源的条，其中至少一条与CMOS对的MOS晶体管的源极区域接触。 为了允许模拟部件对由数字部件在基板中感应的噪声不敏感的集成电路的设计，并且其中可以减少待机模式下的数字部件的电流吸收，电池 库还提供了一组单元，其中提供至少一个额外的迹线，其限定用于连接到外部并与CMOS对的MOS晶体管的体区接触的附加条。
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