公开(公告)号：US20180061775A1

公开(公告)日：2018-03-01

申请号：US15253782

申请日：2016-08-31

Applicant: QUALCOMM Incorporated

Inventor： Mario Velez ,  Niranjan Sunil Mudakatte ,  Changhan Yun ,  David Berdy ,  Shiqun Gu ,  Jonghae Kim ,  Chengjie Zuo

IPC: H01L23/00 ,  H01L49/02 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A device that includes a single substrate layer, a plurality of interconnects over the single substrate layer, the plurality of interconnects configured to operate as at least one passive component, a first die coupled to the single substrate layer and the plurality of interconnects, and an encapsulation layer that at least partially encapsulates the first die and the plurality of interconnects configured to operate as at least one passive component. In some implementations, the single substrate layer, the first die and the encapsulation layer comprise an overall thickness of about 225 microns (μm) or less. In some implementations, the single substrate layer comprises a thickness of about 75 microns (μm) or less.

公开(公告)号：US09379802B2

公开(公告)日：2016-06-28

申请号：US14684072

申请日：2015-04-10

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Mario F. Velez ,  Jonghae Kim

IPC: H04B1/06 ,  H04B1/44 ,  H03C7/02 ,  H01Q11/12 ,  H04M1/00 ,  H04B7/08 ,  H04B1/16 ,  H04B1/00 ,  H04B1/18

CPC classification number: H04B7/0805 ,  H04B1/005 ,  H04B1/16 ,  H04B1/18 ,  H04B7/0825

Abstract: A diversity receiver switch includes at least one second stage switch configured to communicate with a transceiver. The diversity receiver switch may also include at least one first stage switch coupled between a diversity receiver antenna and the second stage switch(es). The first stage switch(es) may be configured to handle a different amount of power than the second stage switch(es). The diversity receiver switch may include a bank of second stage switches configured to communicate with a transceiver. A first stage switch may be configured to handle more power than each switch in the bank of second stage switches. Alternatively, the diversity receiver switch include a bank of first stage switches coupled between the diversity receiver antenna and a second stage switch. The second stage switch may be configured to handle more power than each of the first stage switches.

公开(公告)号：US20150035162A1

公开(公告)日：2015-02-05

申请号：US13957462

申请日：2013-08-02

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Lan ,  Chengjie Zuo ,  Mario Francisco Velez ,  Daeik D. Kim ,  David F. Berdy ,  Changhan Yun ,  Robert P. Mikulka ,  Jonghae Kim ,  Matthew M. Nowak

IPC: H01L23/522 ,  G06F17/50 ,  H01L21/768

CPC classification number: H01L23/5226 ,  G06F17/5068 ,  H01F17/0013 ,  H01F41/041 ,  H01F2017/002 ,  H01L21/76897 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/13 ,  H01L28/10 ,  H01L28/40 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/13022 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H05K1/162 ,  H05K1/165 ,  H05K3/4605 ,  H01L2924/00

Abstract: An inductive device that includes a conductive via and a metal layer are disclosed. A particular method of forming an electronic device includes forming a metal layer that contacts a surface of a substrate. The substrate, including the surface, is formed from a substantially uniform dielectric material. The metal layer contacts a conductive via that extends at least partially within the substrate. The metal layer and the conductive via form at least a portion of an inductive device.

Abstract translation: 公开了一种包括导电通孔和金属层的电感器件。 形成电子器件的具体方法包括形成接触衬底表面的金属层。 包括表面的基底由基本均匀的电介质材料形成。 金属层接触至少部分地在衬底内延伸的导电通孔。 金属层和导电通孔形成电感器件的至少一部分。

公开(公告)号：US20140354372A1

公开(公告)日：2014-12-04

申请号：US14019821

申请日：2013-09-06

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Jonghae Kim ,  Daeik D. Kim ,  Mario Francisco Velez ,  Changhan Yun ,  Je-Hsiung Lan ,  Robert P. Mikulka ,  Matthew M. Nowak

IPC: H03H7/46 ,  H03H3/00

CPC classification number: H03H7/463 ,  H03H3/00 ,  Y10T29/4902

Abstract: Systems for reducing magnetic coupling in integrated circuits (ICs) are disclosed. Related components and methods are also disclosed. The ICs have a plurality of inductors. Each inductor generates a magnetic flux that has a discernible axis. To reduce magnetic coupling between the inductors, the flux axes are designed so as to be non-parallel. In particular, by making the flux axes of the inductors non-parallel to one another, magnetic coupling between the inductors is reduced relative to the situation where the flux axes are parallel. This arrangement may be particularly well suited for use in diplexers having a low pass and a high pass filter.

Abstract translation: 公开了用于减小集成电路（IC）中的磁耦合的系统。 还公开了相关的部件和方法。 IC具有多个电感器。 每个电感器产生具有可辨别轴线的磁通量。 为了减小电感器之间的磁耦合，磁通轴被设计成不平行。 特别地，通过使电感器的磁通轴彼此不平行，相对于磁通轴平行的情况，电感器之间的磁耦合减小。 这种布置可以特别适用于具有低通和高通滤波器的双工器。

公开(公告)号：US20140327508A1

公开(公告)日：2014-11-06

申请号：US13887633

申请日：2013-05-06

Applicant: QUALCOMM INCORPORATED

Inventor： Daeik D. Kim ,  Kangho Lee ,  David F. Berdy ,  Mario Francisco Velez ,  Jonghae Kim ,  Je-Hsiung Lan ,  Changhan Yun ,  Niranjan Sunil Mudakatte ,  Robert P. Mikulka

IPC: H01F29/14

CPC classification number: H01F21/06 ,  H01F21/08 ,  H01F27/255

Abstract: An inductor tunable by a variable magnetic flux density component is disclosed. A particular device includes an inductor. The device further includes a variable magnetic flux density component (VMFDC) positioned to influence a magnetic field of the inductor when a current is applied to the inductor.

Abstract translation: 公开了一种由可变磁通密度分量调节的电感器。 特定器件包括电感器。 该装置还包括可变磁通密度分量（VMFDC），其定位成当电流施加到电感器时影响电感器的磁场。

公开(公告)号：US20140197902A1

公开(公告)日：2014-07-17

申请号：US13798733

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Chengjie Zuo ,  Jonghae Kim ,  Mario Francisco Velez ,  Je-Hsiung Lan ,  Daeik D. Kim ,  Changhan Yun ,  David F. Berdy ,  Robert P. Mikulka ,  Matthew M. Nowak ,  Xiangdong Zhang ,  Puay H. See

IPC: H03H7/46 ,  H03H3/00

CPC classification number: H03H7/461 ,  H01F2017/0026 ,  H01F2017/004 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/64 ,  H01L23/66 ,  H01L2924/0002 ,  H03H3/00 ,  H03H7/1758 ,  H03H7/1766 ,  H03H7/1791 ,  H03H7/463 ,  H03H2001/0021 ,  H05K1/0233 ,  H05K1/0306 ,  H05K1/165 ,  H05K2201/09627 ,  H05K2201/09672 ,  H05K2201/10015 ,  H05K2201/10098 ,  Y10T29/49128 ,  H01L2924/00

Abstract: A diplexer includes a substrate having a set of through substrate vias. The diplexer also includes a first set of traces on a first surface of the substrate. The first traces are coupled to the through substrate vias. The diplexer further includes a second set of traces on a second surface of the substrate that is opposite the first surface. The second traces are coupled to opposite ends of the set of through substrate vias. The through substrate vias and the traces also operate as a 3D inductor. The diplexer also includes a capacitor supported by the substrate.

Abstract translation: 双工器包括具有一组通过衬底通孔的衬底。 双工器还包括在衬底的第一表面上的第一组迹线。 第一迹线耦合到贯穿衬底通孔。 双工器还包括与第一表面相对的在衬底的第二表面上的第二组迹线。 第二迹线耦合到该组通过衬底通孔的相对端。 贯通衬底通孔和迹线也作为3D电感器工作。 双工器还包括由基板支撑的电容器。

公开(公告)号：US10171112B2

公开(公告)日：2019-01-01

申请号：US15080472

申请日：2016-03-24

Applicant: QUALCOMM Incorporated

Inventor： Yunfei Ma ,  Chengjie Zuo ,  David Berdy ,  Daeik Kim ,  Changhan Yun ,  Je-Hsiung Lan ,  Mario Velez ,  Niranjan Sunil Mudakatte ,  Robert Mikulka ,  Jonghae Kim

IPC: H01P5/18 ,  H04B1/00 ,  H04B1/04 ,  H04B1/3827 ,  H04B1/40 ,  H04L5/14 ,  H03H7/09 ,  H03H7/46 ,  H01P5/02

Abstract: An RF diplexer is provided that includes a first channel and a second channel. The first channel includes a first primary inductor. Similarly, the second channel includes a second primary inductor. A first directional coupler for the first channel includes a first transformer formed by the first primary inductor and also a first secondary inductor. A first terminal for the first secondary inductor is a coupled port for the first directional coupler. A second directional coupler for the second channel includes a second transformer formed by the second primary inductor and also a second secondary inductor. A first terminal for the second secondary inductor is a coupled port for the second directional coupler.

公开(公告)号：US09837209B2

公开(公告)日：2017-12-05

申请号：US13684072

申请日：2012-11-21

Applicant: QUALCOMM Incorporated

Inventor： Kyu-Pyung Hwang ,  Young K. Song ,  Changhan Yun ,  Dong Wook Kim

IPC: H01G4/00 ,  H01G4/30 ,  H01G4/005 ,  H01G4/232 ,  H01G4/224 ,  H01G4/002 ,  H01G4/012 ,  H01G4/33 ,  H01L23/50

CPC classification number: H01G4/002 ,  H01G4/012 ,  H01G4/33 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/19105 ,  Y10T29/417 ,  H01L2924/00

Abstract: Some novel features pertain to a capacitor structure that includes a first conductive layer, a second conductive layer and a non-conductive layer. The first conductive layer has a first overlapping portion and a second overlapping portion. The second conductive layer has a third overlapping portion, a fourth overlapping portion, and a non-overlapping portion. The third overlapping portion overlaps with the first overlapping portion of the first conductive layer. The fourth overlapping portion overlaps with the second overlapping portion of the first conductive layer. The non-overlapping portion is free of any overlap (e.g., vertical overlap) with the first conductive layer. The non-conductive layer separates the first and second conductive layers. The non-conductive layer electrically insulates the third overlapping portion and the fourth overlapping portion from the first conductive layer.

公开(公告)号：US09813043B2

公开(公告)日：2017-11-07

申请号：US15079789

申请日：2016-03-24

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Daeik D. Kim ,  Je-Hsiung Lan ,  Jonghae Kim ,  Mario Francisco Velez ,  Changhan Yun ,  David F. Berdy ,  Robert P. Mikulka ,  Matthew M. Nowak ,  Xiangdong Zhang ,  Puay H. See

IPC: H03H7/46 ,  H03H3/00 ,  H03H7/01

CPC classification number: H03H7/461 ,  H03H3/00 ,  H03H7/0115 ,  H03H7/463 ,  Y10T29/49016

Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.

公开(公告)号：US20170271266A1

公开(公告)日：2017-09-21

申请号：US15074750

申请日：2016-03-18

Applicant: QUALCOMM Incorporated

Inventor： Daeik Kim ,  Jie Fu ,  Changhan Yun ,  Chin-Kwan Kim ,  Manuel Aldrete ,  Chengjie Zuo ,  Mario Velez ,  Jonghae Kim

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.