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    Low-power clocking for a high-speed memory interface
    21.
    发明授权
    Low-power clocking for a high-speed memory interface 有权

    公开(公告)号：US10169262B2

    公开(公告)日：2019-01-01

    申请号：US15204755

    申请日：2016-07-07

    Applicant: QUALCOMM Incorporated

    Inventor： David West ,  Vaishnav Srinivas ,  Michael Brunolli ,  Jungwon Suh

    IPC: G06F13/00 ,  G06F13/16 ,  G06F13/40 ,  G11C7/22 ,  H03L7/08

    Abstract: Methods, apparatus, and system for use in adaptive communication interfaces are disclosed. An adaptive communication interface is provided, in which a high-speed clock provided in a high-speed mode of operation is suppressed in a low-power mode of operation. In the low-power mode of operation, a low-speed command clock is used for data transfers between a memory device and a system-on-chip, applications processor or other device. A method for operating the adaptive communication interface may include using a first clock signal to control transmissions of commands to a memory device over a command bus. In a first mode of operation, the first clock signal controls data transmissions over the adaptive communication interface. In a second mode of operation, the second clock signal controls data transmissions over the adaptive communication interface. The frequency of the second clock signal may be greater than the frequency of the first clock signal.

    DRAM sub-array level autonomic refresh memory controller optimization
    25.
    发明授权
    DRAM sub-array level autonomic refresh memory controller optimization 有权
    DRAM子阵列级自动刷新内存控制器优化

    公开(公告)号：US09524771B2

    公开(公告)日：2016-12-20

    申请号：US14148515

    申请日：2014-01-06

    Applicant: QUALCOMM Incorporated

    Inventor： Deepti Vijayalakshmi Sriramagiri ,  Jungwon Suh ,  Xiangyu Dong

    IPC: G11C11/406 ,  G06F13/16

    CPC classification number: G11C11/40618 ,  G06F13/1636 ,  G11C11/40603 ,  G11C11/40611

    Abstract: A method of refreshing a dynamic random access memory (DRAM) includes detecting an open page of the DRAM at a row of a DRAM bank within an open sub-array of the DRAM bank. The method also includes delaying issuance of a refresh command to a target refresh row of the DRAM bank when the target refresh row of the DRAM bank is within the open sub-array of the DRAM bank.

    Abstract translation: 一种刷新动态随机存取存储器（DRAM）的方法包括：检测在DRAM存储体的开放子阵列内的DRAM存储体的行的DRAM的打开页面。 该方法还包括当DRAM存储体的目标刷新行位于DRAM存储体的打开子阵列内时，向DRAM存储体的目标刷新行延迟发出刷新命令。

    Refresh scheme for memory cells with next bit table
    29.
    发明授权
    Refresh scheme for memory cells with next bit table 有权
    具有下一位表的存储单元的刷新方案

    公开(公告)号：US09230634B2

    公开(公告)日：2016-01-05

    申请号：US14276452

    申请日：2014-05-13

    Applicant: QUALCOMM Incorporated

    Inventor： Jung Pill Kim ,  Jungwon Suh ,  Xiangyu Dong

    IPC: G06F12/00 ,  G11C11/406 ,  G06F12/02

    CPC classification number: G11C11/406 ,  G06F12/0207 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/40622 ,  G11C2211/4061 ,  G11C2211/4065

    Abstract: A memory refresh control technique allows flexible internal refresh rates based on an external 1× refresh rate and allows skipping a refresh cycle for strong memory rows based on the external 1× refresh rate. A memory controller performs a memory refresh by reading a refresh address from a refresh address counter, reading a weak address from a weak address table and generating a next weak address value based at least in part on a next bit sequence combined with the weak address. The memory controller compares the refresh address to the weak address and to the next weak address value. Based on the comparison, the memory controller selects between skipping a refresh cycle, refreshing the refresh address, refreshing the weak address, and refreshing both the refresh address and the weak address.

    Abstract translation: 存储器刷新控制技术允许基于外部1×刷新率的灵活的内部刷新率，并允许基于外部1×刷新率跳过强存储器行的刷新周期。 存储器控制器通过从刷新地址计数器读取刷新地址，从弱地址表读取弱地址并且至少部分地基于与弱地址组合的下一个比特序列产生下一个弱地址值来执行存储器刷新。 存储器控制器将刷新地址与弱地址和下一个弱地址值进行比较。 基于比较，存储器控制器在跳过刷新周期，刷新刷新地址，刷新弱地址以及刷新刷新地址和弱地址之间进行选择。

    PRIORITY ADJUSTMENT OF DYNAMIC RANDOM ACCESS MEMORY (DRAM) TRANSACTIONS PRIOR TO ISSUING A PER-BANK REFRESH FOR REDUCING DRAM UNAVAILABILITY
    30.
    发明申请
    PRIORITY ADJUSTMENT OF DYNAMIC RANDOM ACCESS MEMORY (DRAM) TRANSACTIONS PRIOR TO ISSUING A PER-BANK REFRESH FOR REDUCING DRAM UNAVAILABILITY 审中-公开
    优先调整动态随机存取存储器（DRAM）交易，以发布每次银行刷新以减少DRAM无法使用

    公开(公告)号：US20150318035A1

    公开(公告)日：2015-11-05

    申请号：US14267966

    申请日：2014-05-02

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangyu Dong ,  Jungwon Suh

    IPC: G11C11/406

    CPC classification number: G06F13/1642

    Abstract: Priority adjustment of dynamic random access memory (DRAM) transactions prior to issuing a per-bank refresh for reducing DRAM unavailability is disclosed. In one aspect, DRAM is refreshed on a per-bank basis. If a queued memory transaction corresponds to a memory bank that will soon be refreshed, the transaction may be delayed if a refresh of the corresponding memory bank begins prior to execution of the transaction. To avoid delaying execution of the transaction while waiting for the corresponding memory bank to be refreshed, a priority of the memory transactions may be adjusted based on a memory bank refresh schedule. The priority of the transaction corresponding to the memory bank to be refreshed may be increased, and the priority of other memory transactions may be decreased, if such an adjustment would avoid or reduce delaying execution due to unavailability of the corresponding memory bank.

    Abstract translation: 公开了在发布用于减少DRAM不可用性的每存储体刷新之前的动态随机存取存储器（DRAM）事务的优先级调整。 在一个方面，DRAM以每个银行为基础刷新。 如果排队的存储器事务对应于将要刷新的存储体，则如果相应的存储体的刷新在执行事务之前开始，则事务可能被延迟。 为了避免在等待相应的存储体被刷新的同时执行事务的延迟，可以基于存储体刷新调度来调整存储器事务的优先级。 可以增加与要刷新的存储体对应的事务的优先级，并且如果这样的调整将避免或减少由于对应的存储体的不可用性而导致的延迟执行，则可以减少其他存储器事务的优先级。

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