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    Pulse control for nonvolatile memory
    22.
    发明授权
    Pulse control for nonvolatile memory 有权
    非易失性存储器的脉冲控制

    公开(公告)号：US09177655B2

    公开(公告)日：2015-11-03

    申请号：US14145962

    申请日：2014-01-01

    Applicant: Rambus Inc.

    Inventor： Mark D. Kellam ,  Brent Steven Haukness ,  Gary B. Bronner ,  Kevin Donnelly

    IPC: G11C16/12 ,  G11C16/10 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C16/0408 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3459

    Abstract: A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.

    Abstract translation: 非易失性存储器件，其使用脉冲控制和休止期来减轻缺陷前体的形成。 第一实施例使用脉冲位线控制，其中当希望改变相关联的存储器单元中的状态时，存储器单元通道与参考电压之间的耦合是脉冲的。 每个脉冲可以选择为小于约20纳秒，而脉冲之间的“休止期”可以在大约一百纳秒或更大的数量级。 由于使用位线控制，所以可以启用非常短的上升时间，可以产生50纳秒或更短的脉冲持续时间。 在其他实施例中，这些方法还可以更一般地应用于其它导体（例如，字线或衬底阱，用于编程或擦除操作）; 也可以使用分段字线或位线，以最小化RC负载并且实现足够短的上升时间以使脉冲稳健。

    SOLID-STATE DRIVE WITH THERMAL ANNEAL FUNCTION
    23.
    发明申请
    SOLID-STATE DRIVE WITH THERMAL ANNEAL FUNCTION 有权

    公开(公告)号：US20240395327A1

    公开(公告)日：2024-11-28

    申请号：US18645875

    申请日：2024-04-25

    Applicant: Rambus Inc.

    Inventor： Gary B. Bronner ,  Brent Steven Haukness ,  Mark A. Horowitz ,  Mark D. Kellam ,  Fariborz Assaderaghi

    IPC: G11C16/06 ,  G11C7/04 ,  G11C13/00 ,  G11C16/26 ,  H01L21/324

    Abstract: Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.

    MEMORY DEVICE AND REPAIR METHOD WITH COLUMN-BASED ERROR CODE TRACKING
    27.
    发明申请
    MEMORY DEVICE AND REPAIR METHOD WITH COLUMN-BASED ERROR CODE TRACKING 有权

    公开(公告)号：US20220171674A1

    公开(公告)日：2022-06-02

    申请号：US17548509

    申请日：2021-12-11

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent Steven Haukness

    IPC: G06F11/10 ,  G11C29/52 ,  G06F12/02

    Abstract: A memory device is disclosed that includes a row of storage locations that form plural columns. The plural columns include data columns to store data and a tag column to store tag information associated with error locations in the data columns. Each data column is associated with an error correction location including an error code bit location. Logic retrieves and stores the tag information associated with the row in response to activation of the row. A bit error in an accessed data column is repaired by a spare bit location based on the tag information.

    Complementary RRAM applications for logic and ternary content addressable memory (TCAM)
    29.
    发明授权
    Complementary RRAM applications for logic and ternary content addressable memory (TCAM) 有权

    公开(公告)号：US09704576B2

    公开(公告)日：2017-07-11

    申请号：US14621171

    申请日：2015-02-12

    Applicant: Rambus Inc.

    Inventor： Scott C. Best ,  Brent Steven Haukness

    IPC: G11C15/04 ,  G11C13/00

    CPC classification number: G11C15/046 ,  G11C13/0002

    Abstract: A ternary content addressable memory (TCAM) cell may include a first resistive memory element, a second resistive memory element, a third resistive memory element, and a first switching element. The first resistive memory element may be disposed between a true data bit line node and a common node. The second resistive memory element may be disposed between a complement data bit line node and the common node. The third resistive element may be coupled to the common node and a word line node. The first switching element may have a control terminal coupled to the common node.

    CONTENT ADDRESSABLE MEMORY
    30.
    发明申请
    CONTENT ADDRESSABLE MEMORY 有权
    内容可寻址内存

    公开(公告)号：US20140153310A1

    公开(公告)日：2014-06-05

    申请号：US14091213

    申请日：2013-11-26

    Applicant: Rambus Inc.

    Inventor： Deepak Chandra Sekar ,  Brent Steven Haukness ,  John Eric Linstadt ,  Scott C. Best

    IPC: G11C15/00 ,  G11C13/00

    CPC classification number: G11C15/00 ,  G11C13/0002 ,  G11C15/046

    Abstract: A content addressable memory can include an array of memory cells having multiple memory elements, such as RRAM elements, to store data based on a plurality resistive states. A common switching device, such as a transistor, can electrically couple a plurality of the multiple memory elements with a matchline during read, write, erase, and search operations. In search operations, the memory cells can receive a search word and selectively discharge a voltage level on the matchline based on the data stored by the memory elements and the search word provided to the memory elements. The voltage level of the matchline can indicate whether the search word matched the data stored in the memory cells. The content addressable memory can potentially have an effective memory cell sizing under 0.5F2 depending on the number of layers of memory cells formed over the switching device.

    Abstract translation: 内容可寻址存储器可以包括具有多个存储器元件（诸如RRAM元件）的存储器单元阵列，以存储基于多个电阻状态的数据。 诸如晶体管的公共开关器件可以在读，写，擦除和搜索操作期间用匹配线电耦合多个多个存储器元件。 在搜索操作中，存储器单元可以接收搜索词，并且基于由存储元件存储的数据和提供给存储器元件的搜索词来选择性地排放匹配线上的电压电平。 匹配线的电压电平可以指示搜索词是否匹配存储在存储单元中的数据。 内容可寻址存储器可能潜在地具有根据在开关器件上形成的存储器单元的层数在0.5F2下的有效存储单元大小。

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