公开(公告)号：US08514583B2

公开(公告)日：2013-08-20

申请号：US12945111

申请日：2010-11-12

Applicant: Roger D. Weekly

Inventor： Roger D. Weekly

IPC: H05K7/02

CPC classification number: H05K7/1061 ,  G06F1/183 ,  H01L2924/15311

Abstract: A processor module socket accommodates processor modules of different sizes with adapters that align smaller-sized modules so that module pins align with desired contact points. The largest supported processor module engages with the socket in a conventional manner without the use of an adapter. Smaller processor modules engage within an adapter that in turn engages in the socket in a manner similar to the largest supported processor module. The contact points of the socket support different sized processor modules by keying logical functions based upon the type of processor module installed in the socket.

Abstract translation: 处理器模块插座可容纳具有不同尺寸的处理器模块，适配器可对准较小尺寸的模块，使模块引脚与所需的接触点对准。 最大的支持的处理器模块以常规方式与插座接合，而不使用适配器。 较小的处理器模块接合在适配器中，该适配器又以类似于最大支持的处理器模块的方式进入插座。 插座的接点通过根据安装在插座中的处理器模块的类型键入逻辑功能来支持不同大小的处理器模块。

公开(公告)号：US20130015573A1

公开(公告)日：2013-01-17

申请号：US13614102

申请日：2012-09-13

Applicant: Yaping Zhou ,  Roger D. Weekly

Inventor： Yaping Zhou ,  Roger D. Weekly

IPC: H01L23/49

CPC classification number: H01L23/49816 ,  H01L23/50 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns.

Abstract translation: 一种用于分配电源和接地引脚以及用于球栅阵列半导体封装的单端或差分信号对的改进的系统和方法。 在某些实施例中，系统使用六边形图案，其中网格可以由多个嵌套的六边形图案表示。

公开(公告)号：US08338948B2

公开(公告)日：2012-12-25

申请号：US12827693

申请日：2010-06-30

Applicant: Roger D. Weekly ,  Yaping Zhou

Inventor： Roger D. Weekly ,  Yaping Zhou

IPC: H01L23/48

CPC classification number: H01L23/49816 ,  H01L23/50 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns.

Abstract translation: 一种用于分配电源和接地引脚以及用于球栅阵列半导体封装的单端或差分信号对的改进的系统和方法。 在某些实施例中，系统使用六边形图案，其中网格可以由多个嵌套的六边形图案表示。

公开(公告)号：US20120081859A1

公开(公告)日：2012-04-05

申请号：US12895623

申请日：2010-09-30

Applicant: Michael A. Christo ,  Julio A. Maldonado ,  Roger D. Weekly ,  Tingdong Zhou

Inventor： Michael A. Christo ,  Julio A. Maldonado ,  Roger D. Weekly ,  Tingdong Zhou

IPC: H05K1/14

CPC classification number: H05K1/112 ,  H05K1/0263 ,  H05K1/0296 ,  H05K1/115 ,  H05K3/3436 ,  H05K2201/0355 ,  H05K2201/1028 ,  Y10T29/49128 ,  Y10T29/49155

Abstract: Power may be supplied to an electronic module according to various techniques. In one general implementation, for example, a system for supping power to an electronic module may include a printed circuit board, the electronic module, and a conductive foil. The board may include a number of contact locations on a first side, with at least one of the contact locations electrically coupled to a via to a second side of the board. The electronic module may be electrically coupled to the contact locations on the first side of the board and receive electrical power through the at least one contact location electrically coupled to a via. The foil may be adapted to convey electrical power for the electronic module and electrically coupled on the second side of circuit board to at least the via electrically coupled to a contact location that receives electrical power for the electronic module.

Abstract translation: 可以根据各种技术向电子模块供电。 在一般的实施方案中，例如，用于对电子模块的电力的系统可以包括印刷电路板，电子模块和导电箔。 板可以包括在第一侧上的多个接触位置，其中至少一个接触位置电耦合到通孔到板的第二侧。 电子模块可以电耦合到板的第一侧上的接触位置，并且通过电耦合到通孔的至少一个接触位置接收电力。 箔可以适于传送用于电子模块的电力并且电耦合到电路板的第二侧上至少通过电气耦合到接收用于电子模块的电力的接触位置的通孔。

公开(公告)号：US07987399B2

公开(公告)日：2011-07-26

申请号：US11758708

申请日：2007-06-06

Applicant: Richard Dono ,  Roger D. Weekly

Inventor： Richard Dono ,  Roger D. Weekly

IPC: G01R31/28

CPC classification number: G01R31/318533

Abstract: A test card system for use in product development includes a device under test (DUT). The DUT comprises: a mount plane; a power input port coupled to the mount plane; a JTAG input port coupled to the mount plane; a clock signal distribution network coupled to the JTAG input port; a plurality of latches coupled to the clock signal distribution network and the power input port; and an output port coupled to the plurality of latches. A test card (TC) couples to the DUT, comprising: a JTAG interface coupled to the DUT JTAG input port and configured to provide test data to the DUT; a clock module coupled to the DUT clock signal distribution network and configured to generate a clock signal; and an analysis module coupled to the DUT output port and configured to receive data from the DUT.

Abstract translation: 用于产品开发的测试卡系统包括被测设备（DUT）。 DUT包括：安装平面; 耦合到所述安装平面的电力输入端口; 耦合到安装平面的JTAG输入端口; 耦合到JTAG输入端口的时钟信号分配网络; 耦合到时钟信号分配网络和电力输入端口的多个锁存器; 以及耦合到所述多个锁存器的输出端口。 测试卡（TC）耦合到DUT，包括：耦合到DUT JTAG输入端口并被配置为向DUT提供测试数据的JTAG接口; 时钟模块，其耦合到所述DUT时钟信号分配网络并且被配置为生成时钟信号; 以及耦合到DUT输出端口并被配置为从DUT接收数据的分析模块。

公开(公告)号：US07920978B2

公开(公告)日：2011-04-05

申请号：US12262021

申请日：2008-10-30

Applicant: Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao G. Truong ,  Roger D. Weekly

Inventor： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao G. Truong ,  Roger D. Weekly

IPC: G06F1/26 ,  G06F11/30

CPC classification number: G06F1/305

Abstract: A circuit for detecting noise events in a system with time variable operating points is provided. A first voltage, which is averaged over time, is compared to a second voltage. A signal is generated to instruct circuits within a processor to initiate actions to keep a voltage from drooping further.

Abstract translation: 提供了一种用于检测具有时间可变操作点的系统中的噪声事件的电路。 将经过时间平均的第一电压与第二电压进行比较。 生成信号以指示处理器内的电路以启动动作以使电压进一步下降。

公开(公告)号：US07917328B2

公开(公告)日：2011-03-29

申请号：US12194606

申请日：2008-08-20

Applicant: Jon A. Casey ,  Michael S. Floyd ,  Soraya Ghiasi ,  Kenneth C. Marston ,  Jennifer V. Muncy ,  Malcom S. Ware ,  Roger D. Weekly

Inventor： Jon A. Casey ,  Michael S. Floyd ,  Soraya Ghiasi ,  Kenneth C. Marston ,  Jennifer V. Muncy ,  Malcom S. Ware ,  Roger D. Weekly

IPC: G06F19/00

CPC classification number: G06F11/3058

Abstract: Monitoring temperature excursions an assembly experiences over a life of the assembly is provided. A determination is made as to whether the assembly has been in service beyond a predetermined end of life objective. Responsive to the assembly failing to be in service beyond the predetermined end of life objective, a new temperature value associated with the assembly is read. A modifier value for a figure of merit (FOM) value is computed and added to a cumulative figure of merit value. The cumulative figure of merit value is compared to a cumulative stress figure of merit budget. Responsive to the cumulative figure of merit value exceeding the cumulative stress figure of merit budget, an identified stress management solution is implemented.

Abstract translation: 提供了组装过程中组装体验的温度偏移。 确定组件是否已经超出预定寿命目标的使用。 响应于组装不能超过预定寿命目标的服务，读取与组件相关联的新的温度值。 计算品质因数（FOM）值的修饰符值，并将其添加到累积品质因数值。 将累积的绩效值与累积压力的绩效预算进行比较。 响应累积绩效值超过累积压力的绩效预算数量，实施了一个确定的压力管理解决方案。

公开(公告)号：US07765504B2

公开(公告)日：2010-07-27

申请号：US11829179

申请日：2007-07-27

Applicant: Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Roger D. Weekly

Inventor： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Roger D. Weekly

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  H05K1/0216 ,  H05K1/115 ,  H05K3/0005 ,  H05K2201/09636

Abstract: A design method and system for minimizing blind via current loops provides for improvement of electrical interconnect structure design without requiring extensive electromagnetic analysis. Other vias in the vicinity of a blind via carrying a critical signal are checked for suitability to conduct return current corresponding to the critical signal that is disrupted by the transition from a layer between two metal planes to another layer. The distance to the return current via(s) is checked and the design is adjusted to reduce the distance if the distance is greater than a specified threshold. If the blind via transition is to an external layer, suitable vias connect the reference plane at the internal end of the blind via to an external terminal. If the transition is between internal layers, suitable vias are vias that connect the two reference planes surrounding the reference plane traversed by the blind via.

Abstract translation: 用于最小化盲通过电流回路的设计方法和系统提供了电互连结构设计的改进，而不需要广泛的电磁分析。 检查通过携带关键信号的盲目附近的其他通孔是否​​适合于进行对应于由两个金属平面之间的层到另一层之间的过渡而被破坏的关键信号的返回电流。 检查通过（s）的返回电流的距离，并且如果距离大于指定的阈值，则设计被调整以减小距离。 如果盲目通过转换到外部层，合适的通孔将盲通孔内部的参考平面连接到外部端子。 如果过渡在内层之间，合适的通孔是连接围绕由盲孔通过的参考平面的两个参考平面的通孔。

公开(公告)号：US07607028B2

公开(公告)日：2009-10-20

申请号：US11420820

申请日：2006-05-30

Applicant: Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao G. Truong ,  Roger D. Weekly

Inventor： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Bao G. Truong ,  Roger D. Weekly

IPC: G06F1/26

CPC classification number: G06F1/26

Abstract: A system for mitigating power supply and power distribution system noise response by throttling execution units based upon voltage sensing in a circuit is provided. A sensing unit senses the voltage of a circuit. The sensing unit determines if the execution of another execution unit will cause the circuit voltage to drop below a threshold level. In response to a determination that the execution of another execution unit will cause the circuit voltage to drop below the threshold level, the execution unit is throttled.

Abstract translation: 提供了一种通过基于电路中的电压感测的节流执行单元来减轻电源和配电系统噪声响应的系统。 感测单元感测电路的电压。 感测单元确定另一个执行单元的执行是否会导致电路电压降至阈值以下。 响应于确定另一执行单元的执行将导致电路电压降低到阈值水平以下，执行单元被调节。

公开(公告)号：US20090193383A1

公开(公告)日：2009-07-30

申请号：US12021363

申请日：2008-01-29

Applicant: Michael A. Christo ,  Julio A. Maldonado ,  Roger D. Weekly ,  Tingdong Zhou

Inventor： Michael A. Christo ,  Julio A. Maldonado ,  Roger D. Weekly ,  Tingdong Zhou

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  H05K1/0237 ,  H05K3/0005 ,  H05K2201/09236 ,  H05K2201/09672

Abstract: An auto routing method and system provides optimized circuit routing while maintaining proper reference return paths for critical signals. Critical signal paths are auto-routed simultaneously with corresponding reference return paths, and the reference return paths can be merged into reference planes if they are adjacent to regions connected to the same reference net. The reference return paths may be in a plane adjacent to the signal path plane in the same channel, or the reference returns may be routed in adjacent channels in the same plane as the signal path. A check may be performed on endpoints of each critical signal path to determine whether a reference return via is present within a proximity tolerance of the signal path endpoints, and a reference return via placed if not.

Abstract translation: 自动路由方法和系统提供优化的电路路由，同时为关键信号保留适当的参考返回路径。 临界信号路径与对应的参考返回路径同时自动路由，并且如果参考返回路径与连接到相同参考网络的区域相邻，则它们可以合并到参考平面中。 参考返回路径可以在与相同信道中的信号路径平面相邻的平面中，或者参考返回可以在与信号路径相同的平面中的相邻信道中路由。 可以在每个关键信号路径的端点上执行检查，以确定参考返回通道是否存在于信号路径端点的接近容限内，如果不是则通过放置参考返回。