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公开(公告)号：US09514827B1
公开(公告)日：2016-12-06
申请号：US15018925
申请日：2016-02-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Wan Nam , Doo-Hyun Kim , Dae-Seok Byeon , Chi-Weon Yoon
CPC classification number: G06F3/0619 , G06F3/061 , G06F3/0644 , G06F3/0655 , G06F3/0688 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/16 , G11C16/26 , G11C16/34 , G11C16/3459 , H01L27/11582
Abstract: A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.
Abstract translation: 如下提供存储器件。 存储单元区域包括多个块，每个块包括多个NAND串。 控制逻辑基于相对于存储器单元区域的第一边缘的第一距离的较小距离和相对于存储器单元区域的第二边缘的第二距离，将多个块划分为多个块区域，以及 使用用于该操作的多个偏置操作参数组来控制在存储单元区域上执行的操作。 每个偏差集合与块区域之一相关联。
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22.发明授权Resistive memory device, resistive memory system and method of operating the resistive memory device 有权电阻式存储器件，电阻式存储器系统和操作电阻式存储器件的方法公开(公告)号：US09449686B2
公开(公告)日：2016-09-20
申请号：US14743488
申请日：2015-06-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyo-Jin Kwon , Yeong-Taek Lee , Dae-Seok Byeon
CPC classification number: G11C13/004 , G11C11/1655 , G11C11/1657 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/0069
Abstract: A method of operating a resistive memory device and a resistive memory system including a resistive memory device is for a resistive memory device including a plurality of bit lines and at least one dummy bit line. The method of operating the resistive memory device includes detecting a first address accompanying a first command, generating a plurality of inhibit voltages for biasing non-selected lines, and providing to a first dummy bit line a first inhibit voltage selected from among the plurality of inhibit voltages based on a result of detecting the first address.
Abstract translation: 一种操作电阻式存储器件和包括电阻性存储器件的电阻式存储器系统的方法是用于包括多个位线和至少一个虚拟位线的电阻式存储器件。 操作电阻式存储器件的方法包括检测伴随第一命令的第一地址，产生用于偏置非选择线路的多个禁止电压，以及向第一伪位线提供从多个禁止中选择的第一禁止电压 基于检测到第一地址的结果的电压。
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公开(公告)号：US09384832B2
公开(公告)日：2016-07-05
申请号：US14791636
申请日：2015-07-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyo-Jin Kwon , Yeong-Taek Lee , Dae-Seok Byeon
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C11/1673 , G11C11/56 , G11C13/0004 , G11C13/0007 , G11C2213/72
Abstract: A method is for operating a memory device including a plurality of memory cells disposed in regions where a plurality of first signal lines and a plurality of second signal lines cross each other. The method includes applying an initial voltage to the plurality of first signal lines, floating the plurality of first signal lines to which the initial voltage is applied, applying a second inhibit voltage to the plurality of second signal lines, and increasing voltage levels of the plurality of first signal lines to a first inhibit voltage level via capacitive coupling between the plurality of first signal lines which are floated and the plurality of second signal lines to which the second inhibit voltage is applied.
Abstract translation: 一种用于操作存储器件的方法，该存储器件包括设置在多个第一信号线和多条第二信号线彼此交叉的区域中的多个存储单元。 该方法包括将初始电压施加到多个第一信号线，使施加有初始电压的多条第一信号线浮置，向多条第二信号线施加第二禁止电压，以及增加多个第一信号线的电压电平 的第一信号线通过在浮置的多个第一信号线之间的电容耦合和施加第二禁止电压的多个第二信号线之间的第一禁止电压电平。
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公开(公告)号：US09189174B2
公开(公告)日：2015-11-17
申请号：US13904047
申请日：2013-05-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Han-Jun Lee , Dae-Seok Byeon
CPC classification number: G06F3/0679 , G06F3/061 , G06F3/0638 , G11C5/145 , G11C16/12 , G11C16/30
Abstract: Provided are a nonvolatile memory device and a method for operating the nonvolatile memory device. The method for operating the nonvolatile memory device includes generating a first program voltage, applying the generated first program voltage to a first word line to which a first memory cell is connected for performing a first program operation on the first memory cell, determining whether a number of pulses of a pumping clock signal for generating the first program voltage is greater than or equal to a predetermined critical value n (where n is a natural number), and stopping the performing of the first program operation on the first memory cell when the number of pulses of the pumping clock signal is determined to be greater than or equal to the predetermined critical value n.
Abstract translation: 提供了一种用于操作非易失性存储器件的非易失性存储器件和方法。 用于操作非易失性存储器件的方法包括产生第一编程电压，将产生的第一编程电压施加到连接有第一存储单元的第一字线用于对第一存储器单元执行第一程序操作，确定数字 用于产生第一编程电压的泵浦时钟信号的脉冲大于或等于预定临界值n（其中n是自然数），并且当数量为第一存储器单元的数量时停止执行第一程序操作 泵浦时钟信号的脉冲被确定为大于或等于预定临界值n。
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25.发明授权公开(公告)号：US10170190B2
公开(公告)日：2019-01-01
申请号：US15676778
申请日：2017-08-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Wan Nam , Dae-Seok Byeon , Chi-Weon Yoon , Hae-Suk Shin
Abstract: A method of controlling the operation of a memory controller includes, in a read operation of a non-volatile memory device, the memory controller counting a selected read count of a selected string in a selected memory block and/or counting a non-selected read count of a non-selected string in the selected memory block. The memory controller performs a reclaim operation of the selected memory block when the selected read count and/or the non-selected read count exceeds a read threshold. To move data of the selected memory block to another memory block by the reclaim operation, the memory controller may copy the data of the selected memory block to another block by using a changed page address.
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Patent Agency Ranking
公开(公告)号：US09761315B2
公开(公告)日：2017-09-12
申请号：US15357291
申请日：2016-11-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Wan Nam , Doo-Hyun Kim , Dae-Seok Byeon , Chi-Weon Yoon
IPC: G11C11/34 , G11C16/04 , G11C16/14 , G11C16/16 , G11C16/26 , G11C16/06 , G11C16/34 , G11C16/10 , H01L27/11582 , G11C16/12
Abstract: A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.
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公开(公告)号：US09685227B2
公开(公告)日：2017-06-20
申请号：US14661935
申请日：2015-03-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong-Kyu Lee , Yeong-Taek Lee , Dae-Seok Byeon , Hyun-Kook Park , Hyo-Jin Kwon
CPC classification number: G11C13/004 , G11C7/06 , G11C11/1673 , G11C11/56 , G11C11/5607 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0002 , G11C2013/0054 , G11C2213/71
Abstract: A method of reading a memory device that includes a memory cell that stores data of at least two bits includes determining whether a cell resistance level is no greater than a threshold resistance level. If the cell resistance level is smaller than or equal to the threshold resistance level, then the data is read based on a first factor that is inversely proportional to the cell resistance level. If the cell resistance level is greater than the threshold resistance level, then the data is read based on a second factor that is proportional to the cell resistance level.
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28.发明授权公开(公告)号：US09558822B2
公开(公告)日：2017-01-31
申请号：US14695922
申请日：2015-04-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Kook Park , Yeong-Taek Lee , Dae-Seok Byeon , Yong-Kyu Lee , Hyo-Jin Kwon
CPC classification number: G11C13/0069 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0064 , G11C2013/0045 , G11C2013/0066 , G11C2013/0073 , G11C2013/0076 , G11C2013/0078 , G11C2013/0088 , G11C2013/0092
Abstract: In operating a resistive memory device including a number of memory cells, a write pulse is applied to each of the plurality of memory cells such that each of the memory cells has a target resistance state between a first reference resistance and a second reference resistance higher than the first reference resistance. The resistance of each of the memory cells is read by applying a verify pulse to each of the plurality of memory cells. A verify write current pulse is applied to each of the memory cells that has resistance higher than the second reference resistance, and a verify write voltage pulse is applied to each of the memory cells that has resistance lower than the first reference resistance.
Abstract translation: 在操作包括多个存储单元的电阻式存储器件时，将写入脉冲施加到多个存储器单元中的每一个，使得每个存储单元具有第一参考电阻和第二参考电阻之间的目标电阻状态， 第一个参考电阻。 通过对多个存储单元中的每一个应用验证脉冲来读取每个存储单元的电阻。 将验证写入电流脉冲施加到具有高于第二参考电阻的电阻的每个存储器单元，并且将验证写电压脉冲施加到具有低于第一参考电阻的电阻的每个存储单元。
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公开(公告)号：US09558821B2
公开(公告)日：2017-01-31
申请号：US14645701
申请日：2015-03-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Kook Park , Dae-Seok Byeon , Yeong-Taek Lee , Hyo-Jin Kwon , Yong-Kyu Lee
CPC classification number: G11C13/0069 , G11C11/1659 , G11C11/1675 , G11C11/5607 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0064 , G11C13/0097 , G11C2013/0076 , G11C2213/71
Abstract: Provided are a resistive memory device and a method of the resistive memory device. The method of operating the resistive memory device includes performing a pre-read operation on memory cells in response to a write command; performing an erase operation on one or more first memory cells on which a reset write operation is to be performed, determined based on a result of comparing pre-read data from the pre-read operation with write data; and performing set-direction programming on at least some memory cells from among the erased one or more first memory cells and on one or more second memory cells on which a set write operation is to be performed.
Abstract translation: 提供了电阻式存储器件和电阻式存储器件的方法。 操作电阻式存储器件的方法包括：响应写入命令对存储器单元执行预读取操作; 基于将来自预读取操作的预读数据与写数据进行比较确定的一个或多个要执行复位写操作的第一存储单元执行擦除操作; 并且对被擦除的一个或多个第一存储器单元中的至少一些存储器单元以及要执行设定写入操作的一个或多个第二存储器单元执行设置方向编程。
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公开(公告)号：US09536605B2
公开(公告)日：2017-01-03
申请号：US14806780
申请日：2015-07-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Kook Park , Yeong-Taek Lee , Dae-Seok Byeon , Bo-Geun Kim
CPC classification number: G11C13/004 , G11C11/1659 , G11C11/1673 , G11C11/5607 , G11C11/5678 , G11C11/5685 , G11C13/0061 , G11C2013/0054 , G11C2213/71 , G11C2213/77
Abstract: Provided are a resistive memory device including a plurality of memory cells, and a method of operating the resistive memory device. The resistive memory device includes a sensing circuit connected to a first signal line, to which a memory cell is connected, the sensing circuit sensing data stored in the memory cell based on a first reference current; and a reference time generator for generating a reference time signal that determines a time point when a result of the sensing is to be output, based on the first reference current.
Abstract translation: 提供了包括多个存储单元的电阻式存储器件以及操作该电阻式存储器件的方法。 电阻式存储器件包括连接到存储单元连接到的第一信号线的感测电路，感测电路基于第一参考电流感测存储在存储器单元中的数据; 以及参考时间发生器，用于产生基于所述第一参考电流确定所述感测的结果的时间点的参考时间信号。
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