公开(公告)号：US10114549B2

公开(公告)日：2018-10-30

申请号：US15073373

申请日：2016-03-17

Applicant: Sandisk Technologies LLC

Inventor： Idan Alrod ,  Eran Sharon ,  Ariel Navon

IPC: G06F3/06 ,  G11C29/52 ,  G06F11/10 ,  G11C16/34

Abstract: A device includes a memory and a controller including a data shaping engine. The data shaping engine is configured to apply a mapping to input data that includes one or more m-tuples of bits to generate transformed data. The transformed data includes one or more n-tuples of bits, and n is greater than m. A relationship of a gray coding of m-tuples to a gray coding of n-tuples is indicated by the mapping. The input data includes a first number of bit values that represent a particular logical state, and the transformed data includes a second number of bit values that represent the particular logical state, the second number of bit values being less than the first number of bit values.

公开(公告)号：US20180287634A1

公开(公告)日：2018-10-04

申请号：US15475602

申请日：2017-03-31

Applicant: SanDisk Technologies LLC

Inventor： Rami Rom ,  Idan Goldenberg ,  Alexander Bazarsky ,  Eran Sharon ,  Ran Zamir ,  Idan Alrod ,  Stella Achtenberg

IPC: H03M13/11 ,  H03M13/00

CPC classification number: H03M13/118 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0688 ,  G06F11/10 ,  G06F11/1048 ,  H03M13/1102 ,  H03M13/1125 ,  H03M13/116 ,  H03M13/3715 ,  H03M13/616 ,  H03M13/6516 ,  H03M13/6566

Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.

公开(公告)号：US10089177B2

公开(公告)日：2018-10-02

申请号：US15061246

申请日：2016-03-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Alexander Bazarsky ,  Ran Zamir ,  Eran Sharon ,  Idan Alrod

IPC: H03M13/00 ,  G06F11/10 ,  G06F3/06 ,  H03M13/11 ,  H03M13/37 ,  G11C29/00 ,  H03M13/15 ,  H03M13/29 ,  G11C16/34 ,  G11C29/52 ,  G11C29/04

Abstract: An apparatus includes a memory die including a group of storage elements and one or more unallocated redundant columns. A number of the unallocated redundant columns is based on a number of one or more bad columns of the memory die. The apparatus further includes a controller coupled to the memory. The controller is configured to receive data and redundancy information associated with the data from the memory. The data includes a first bit, and the redundancy information includes a second bit. The redundancy information is sensed from the one or more unallocated redundant columns and has a size that is based on the number of one or more bad columns. The controller is further configured to determine a value of the first bit based on one or more parity check conditions associated with the second bit.

公开(公告)号：US10083069B2

公开(公告)日：2018-09-25

申请号：US13928774

申请日：2013-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Seungjune Jeon ,  Idan Alrod ,  Eran Sharon ,  Dana Lee

IPC: G11C29/00 ,  G06F11/07 ,  G11C29/02 ,  G11C16/34

CPC classification number: G06F11/0751 ,  G11C16/3404 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028

Abstract: A data storage device includes a non-volatile memory and a controller. The non-volatile memory includes a word line coupled to a plurality of storage elements. A method includes detecting a condition associated with a defect in the word line. A first subset of the plurality of storage elements and a second subset of the plurality of storage elements are determined based on an estimated location of the defect. The method further includes determining a first read threshold for the first subset and a second read threshold for the second subset.

公开(公告)号：US20170255512A1

公开(公告)日：2017-09-07

申请号：US15252753

申请日：2016-08-31

Applicant: SanDisk Technologies LLC

Inventor： Ran Zamir ,  Alexander Bazarsky ,  Eran Sharon ,  Idan Alrod

IPC: G06F11/10 ,  H03M13/35 ,  G06F3/06 ,  G11C29/52

CPC classification number: H03M13/353 ,  G06F11/1012 ,  G06F11/108 ,  G11C29/52 ,  H03M13/1102 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/27 ,  H03M13/2909 ,  H03M13/618

Abstract: A non-volatile memory system may be configured to generate a codeword with first-type parity bits and one or more second-type parity bits. If a storage location in which the codeword is to be stored includes one or more bad memory cells, the bit sequence of the codeword may be arranged so that at least some of the second-type parity bits are stored in the bad memory cells. During decoding, a first set of syndrome values may be determined for a first set of check nodes and a second set of syndrome values may be determined for a second set of check nodes. In some examples, a syndrome weight used for determining if convergence is achieved may be calculated using check nodes that are unassociated with the second-type parity bits.

公开(公告)号：US09640253B2

公开(公告)日：2017-05-02

申请号：US15204265

申请日：2016-07-07

Applicant: SanDisk Technologies LLC

Inventor： Kevin Michael Conley ,  Raul-Adrian Cernea ,  Eran Sharon ,  Idan Alrod

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/34 ,  G11C16/08 ,  G06F11/10 ,  G11C16/04

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1012 ,  G06F11/1068 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/107 ,  G11C16/3459 ,  G11C29/52

Abstract: A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements.

公开(公告)号：US20160314834A1

公开(公告)日：2016-10-27

申请号：US15204265

申请日：2016-07-07

Applicant: SanDisk Technologies LLC

Inventor： Kevin Michael Conley ,  Raul-Adrian Cernea ,  Eran Sharon ,  Idan Alrod

IPC: G11C11/56 ,  G11C16/08 ,  G11C16/04 ,  G11C16/34

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1012 ,  G06F11/1068 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/107 ,  G11C16/3459 ,  G11C29/52

Abstract: A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements.

公开(公告)号：US10459787B2

公开(公告)日：2019-10-29

申请号：US15709769

申请日：2017-09-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Damian Yurzola ,  Eran Sharon ,  Idan Alrod ,  Michael Altshuler ,  Madhuri Kotagiri ,  Rajeev Nagabhirava

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52

Abstract: In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns.

公开(公告)号：US10355712B2

公开(公告)日：2019-07-16

申请号：US15475602

申请日：2017-03-31

Applicant: SanDisk Technologies LLC

Inventor： Rami Rom ,  Idan Goldenberg ,  Alexander Bazarsky ,  Eran Sharon ,  Ran Zamir ,  Idan Alrod ,  Stella Achtenberg

IPC: H03M13/11 ,  G06F11/10 ,  G06F3/06 ,  H03M13/00 ,  H03M13/37

Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.

公开(公告)号：US20180254090A1

公开(公告)日：2018-09-06

申请号：US15816546

申请日：2017-11-17

Applicant: SanDisk Technologies LLC

Inventor： Deepanshu Dutta ,  Idan Alrod ,  Huai-Yuan Tseng ,  Amul Desai ,  Jun Wan ,  Ken Cheah ,  Sarath Puthenthermadam

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/26

CPC classification number: G11C16/3413 ,  G11C8/08 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/1202

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.