公开(公告)号：US20200286905A1

公开(公告)日：2020-09-10

申请号：US16291577

申请日：2019-03-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James KAI ,  Murshed CHOWDHURY ,  Koichi MATSUNO ,  Johann ALSMEIER

IPC: H01L27/11556 ,  H01L23/538 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L23/00 ,  H01L25/18 ,  H01L23/498 ,  H01L23/532

Abstract: A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.

公开(公告)号：US20200251488A1

公开(公告)日：2020-08-06

申请号：US16388054

申请日：2019-04-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki IWAI ,  Makoto KOTO ,  Sayako NAGAMINE ,  Ching-Huang LU ,  Wei ZHAO ,  Yanli ZHANG ,  James KAI

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L21/762

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory pillar structures extending through the alternating stack. Each of the memory pillar structures includes a respective memory film and a respective vertical semiconductor channel Dielectric cores contact an inner sidewall of a respective one of the vertical semiconductor channels. A drain-select-level isolation structure laterally extends along a first horizontal direction and contacts straight sidewalls of the dielectric cores at a respective two-dimensional flat interface. The memory pillar structures may be formed on-pitch as a two-dimensional periodic array, and themay drain-select-level isolation structure may cut through upper portions of the memory pillar structures to minimize areas occupied by the drain-select-level isolation structure. maymay

公开(公告)号：US20170365613A1

公开(公告)日：2017-12-21

申请号：US15279959

申请日：2016-09-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Marika GUNJI-YONEOKA ,  Atsushi SUYAMA ,  Jayavel PACHAMUTHU ,  Tsuyoshi HADA ,  Daewung KANG ,  Murshed CHOWDHURY ,  James KAI ,  Hiro KINOSHITA ,  Tomoyuki OBU ,  Luckshitha Suriyasena LIYANAGE

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a semiconductor substrate. Memory openings are formed through the alternating stack. An optional silicon-containing epitaxial pedestal and a memory film are formed in each memory opening. After forming an opening through a bottom portion of the memory film within each memory opening, a germanium-containing semiconductor layer and a dielectric layer is formed in each memory opening. Employing the memory film and the dielectric layer as a crucible, a liquid phase epitaxy anneal is performed to convert the germanium-containing semiconductor layer into a germanium-containing epitaxial channel layer. A dielectric core and a drain region can be formed over the dielectric layer. The germanium-containing epitaxial channel layer is single crystalline, and can provide a higher charge carrier mobility than a polysilicon channel.

公开(公告)号：US20170179154A1

公开(公告)日：2017-06-22

申请号：US15269294

申请日：2016-09-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoko FURIHATA ,  Jixin YU ,  Hiroyuki OGAWA ,  James KAI ,  Jin LIU ,  Johann ALSMEIER

IPC: H01L27/115 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0288 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

公开(公告)号：US20240127864A1

公开(公告)日：2024-04-18

申请号：US18350573

申请日：2023-07-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masaaki HIGASHITANI ,  James KAI ,  Johann ALSMEIER

IPC: G11C5/06 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C5/063 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A memory device includes a first memory block containing first word lines and a first source layer segment, and a second memory block containing second word lines and a second source layer segment which is electrically isolated from the first source layer segment. The first word lines in the first memory block are electrically connected to the respective second word lines in the second memory block.

公开(公告)号：US20230044232A1

公开(公告)日：2023-02-09

申请号：US17556298

申请日：2021-12-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James KAI ,  Yuki MIZUTANI ,  Hisakazu OTOI ,  Masaaki HIGASHITANI ,  Hiroyuki OAGAWA

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/48 ,  G11C8/14

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

公开(公告)号：US20210210503A1

公开(公告)日：2021-07-08

申请号：US17106792

申请日：2020-11-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi MATSUNO ,  James KAI ,  Jixin YU ,  Johann ALSMEIER ,  Yoshitaka OTSU

IPC: H01L27/11575 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11582 ,  H01L21/768

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack, wherein each of the memory stack structures comprises a vertical semiconductor channel and a vertical stack of memory elements, a dielectric moat structure vertically extending through the alternating stack and including an annular dielectric plate portion at each level of the electrically conductive layers that laterally surrounds a respective dielectric material plate, and an interconnection via structure laterally surrounded by the dielectric moat structure and vertically extending through each insulating layer within the alternating stack. Each of the annular dielectric plate portions includes a continuous inner sidewall including a plurality of laterally-convex and vertically-planar inner sidewall segments that are adjoined to each other, and a continuous outer sidewall including a plurality of laterally-convex and vertically-planar outer sidewall segments that are adjoined to each other.

公开(公告)号：US20200258904A1

公开(公告)日：2020-08-13

申请号：US16816691

申请日：2020-03-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James KAI ,  Ching-Huang LU ,  Murshed CHOWDHURY ,  Johann ALSMEIER

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11558 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11529

Abstract: A three-dimensional memory device may include an alternating stack of insulating layers and spacer material layers formed over a carrier substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures are formed through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. Drain regions and bit lines can be formed over the memory stack structures to provide a memory die. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A bonding pad can be formed on the source layer.

公开(公告)号：US20200258817A1

公开(公告)日：2020-08-13

申请号：US16829667

申请日：2020-03-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Teruo OKINA ,  Akio NISHIDA ,  James KAI

IPC: H01L23/48 ,  H01L25/065 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/00

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. A pass-through via structure vertically extends through a dielectric material portion that is adjacent to the alternating stack. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A backside bonding pad or bonding wire is formed to be electrically connected to the pass-through via structure.

公开(公告)号：US20200258816A1

公开(公告)日：2020-08-13

申请号：US16829591

申请日：2020-03-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Teruo OKINA ,  Akio NISHIDA ,  James KAI

IPC: H01L23/48 ,  H01L25/065 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/00

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. A pass-through via structure vertically extends through a dielectric material portion that is adjacent to the alternating stack. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A backside bonding pad or bonding wire is formed to be electrically connected to the pass-through via structure.