公开(公告)号：US20230417687A1

公开(公告)日：2023-12-28

申请号：US17808674

申请日：2022-06-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shogo TOMITA ,  Tatsuya HINOUE ,  Michiaki SANO

IPC: G01N23/18 ,  G01N23/083 ,  G01N23/20 ,  H01L21/66

CPC classification number: G01N23/18 ,  G01N23/083 ,  G01N23/20 ,  H01L22/12 ,  G01N2223/6116 ,  G01N2223/646 ,  G01N2223/401 ,  H01L27/11556

Abstract: Systems and methods for non-destructive inspection of semiconductor devices, such as three-dimensional NAND memory device, using reflective X-ray microscope computed tomographic (CT) imaging. An X-ray microscope directs a focused beam of X-ray radiation at an oblique angle onto the surface of a semiconductor wafer such that the beam passes through device structures and at least a portion of the beam is reflected by a semiconductor substrate of the wafer and detected by an X-ray detector. The wafer may be rotated about a rotation axis to obtain X-ray images of a region-of-interest (ROI) at different projection angles. A processing unit uses detected X-ray image data obtained by the X-ray detector at the different projection angles to generate a CT reconstructed image of the ROI. The CT reconstructed image may enable inspection of internal structural features, including embedded defects, in the semiconductor device in a non-destructive manner

公开(公告)号：US20220406720A1

公开(公告)日：2022-12-22

申请号：US17351811

申请日：2021-06-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tatsuya HINOUE ,  Naoki TAKEGUCHI ,  Masanori TSUTSUMI ,  Seiji SHIMABUKURO

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are removed such that a vertical layer stack including a first-type electrically conductive layer, a seamed insulating layer, and a second-type electrically conductive layer are formed in each lateral recess. Memory opening fill structures including a respective vertical stack of memory elements is formed through the insulating layers and the layer stacks. Access points for providing an etchant for removing the sacrificial material layers may be provided by memory openings, contact via cavities or backside trenches.

公开(公告)号：US20220352199A1

公开(公告)日：2022-11-03

申请号：US17523418

申请日：2021-11-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yusuke MUKAE ,  Naoki TAKEGUCHI ,  Yujin TERASAWA ,  Tatsuya HINOUE ,  Ramy Nashed Bassely SAID

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, forming a sacrificial memory opening fill structure in the memory opening, replacing the sacrificial material layers with electrically conductive layers, removing the sacrificial memory opening fill structure selective to the electrically conductive layers, and forming a memory opening fill structure the memory opening after replacing the sacrificial material layers with electrically conductive layers and after removing the sacrificial memory opening fill structure. The memory opening fill structure includes a memory film and a vertical semiconductor channel.

公开(公告)号：US20220223614A1

公开(公告)日：2022-07-14

申请号：US17146866

申请日：2021-01-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shunsuke TAKUMA ,  Yuji TOTOKI ,  Seiji SHIMABUKURO ,  Tatsuya HINOUE ,  Kengo KAJIWARA ,  Akihiro TOBIOKA

IPC: H01L27/11575 ,  H01L23/522 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11582

Abstract: At least one vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Rows of backside support pillar structures are formed through the at least one vertically alternating sequence. Memory stack structures are formed through the at least one vertically alternating sequence. A two-dimensional array of discrete backside trenches is formed through the at least one vertically alternating sequence. Contiguous combinations of a subset of the backside trenches and a subset of the backside support pillar structures divide the at least one vertically alternating sequence into alternating stacks of insulating layers and sacrificial material layers. The sacrificial material layers are replaced with electrically conductive layers while the backside support pillar structures provide structural support to the insulating layers.

公开(公告)号：US20210408025A1

公开(公告)日：2021-12-30

申请号：US16916476

申请日：2020-06-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tatsuya HINOUE

IPC: H01L27/11556 ,  H01L21/768 ,  H01L27/11582 ,  G11C5/02 ,  G11C5/06

Abstract: In-process source-level material layers including a source-level sacrificial layer is formed over a substrate, and an alternating stack of insulating layers and sacrificial material layers is formed thereabove. Memory openings and backside openings are formed through the alternating stack and into the in-process source-level material layers. Memory opening fill structures are formed in the memory openings. A source cavity is formed by removing the source-level sacrificial layer by introducing an etchant through the backside openings, and a source contact layer in the source cavity. The backside openings are laterally expanded and are merged to form backside trenches. Remaining portions of the sacrificial material layers are replaced with electrically conductive layers through the respective backside trenches.

公开(公告)号：US20210358941A1

公开(公告)日：2021-11-18

申请号：US16876370

申请日：2020-05-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kengo KAJIWARA ,  Atsushi SHIMODA ,  Tatsuya HINOUE ,  Junpei KANAZAWA ,  Masanori TERAHARA

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L21/768

Abstract: A three-dimensional memory device includes a first-tier structure located over a substrate and including a first alternating stack of first insulating layers and first electrically conductive layers. a second-tier structure located over the first-tier structure and including a second alternating stack of second insulating layers and second electrically conductive layers, memory stack structures vertically extending through the first alternating stack and the second alternating stack, primary support pillar structures, and auxiliary support pillar structures vertically extending through the first alternating stack, underlying the second stepped surfaces, and located below a horizontal plane including a bottommost surface of the second alternating stack.

公开(公告)号：US20210005627A1

公开(公告)日：2021-01-07

申请号：US16503884

申请日：2019-07-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tatsuya HINOUE ,  Kengo KAJIWARA ,  Ryosuke ITOU ,  Naohiro HOSODA ,  Yohei MASAMORI ,  Kota FUNAYAMA ,  Keisuke TSUKAMOTO ,  Hirofumi WATATANI

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524

Abstract: First memory openings are formed through a first alternating stack of first insulating layers and first spacer material layers. Each first memory opening is filled with a first memory film, a sacrificial dielectric liner, and a first-tier opening fill material portion. Second memory openings are formed through a second alternating stack of second insulating layers and second spacer material layers. A second memory film is formed in each second memory opening. The first-tier opening fill material portions are removed selective to the sacrificial dielectric liners. The sacrificial dielectric liners are removed selective to the second memory films and the first memory films. A vertical semiconductor channel can be formed on each vertical stack of a first memory film and a second memory film.

公开(公告)号：US20200020715A1

公开(公告)日：2020-01-16

申请号：US16242245

申请日：2019-01-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ryo NAKAMURA ,  Yu UEDA ,  Tatsuya HINOUE ,  Shigehisa INOUE ,  Genta MIZUNO ,  Masanori TSUTSUMI

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L21/28 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes respective charge storage elements and a respective vertical semiconductor channel contacting an inner sidewall of the respective charge storage elements. The sacrificial material layers are replaced with electrically conductive layers. A polycrystalline aluminum oxide blocking dielectric layer is provided between each charge storage element and a neighboring one of the electrically conductive layers. The polycrystalline aluminum oxide blocking dielectric layer is formed by: depositing an amorphous aluminum oxide layer, converting the amorphous aluminum oxide layer into an in-process polycrystalline aluminum oxide blocking dielectric layer, and by thinning the in-process polycrystalline aluminum oxide blocking dielectric layer.

公开(公告)号：US20190287982A1

公开(公告)日：2019-09-19

申请号：US16020088

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tatsuya HINOUE ,  Tomoyuki OBU ,  Tomohiro UNO ,  Yusuke MUKAE ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Adarsh RAJASHEKHAR

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11529 ,  H01L27/11573

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each of the electrically conductive layers includes a stack of a compositionally graded diffusion barrier and a metal fill material portion, and the compositionally graded diffusion barrier includes a substantially amorphous region contacting the interface between the compositionally graded diffusion barrier and a substantially crystalline region that is spaced from the interface by the amorphous region. The substantially crystalline region effectively blocks atomic diffusion, and the amorphous region induces formation of large grains during deposition of the metal fill material portions.