公开(公告)号：US20230352525A1

公开(公告)日：2023-11-02

申请号：US18340650

申请日：2023-06-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Peter MOENS ,  Gordon M. GRIVNA ,  Yusheng LIN

IPC: H01L29/06 ,  H01L25/07 ,  H01L29/20 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L25/071 ,  H01L29/2003 ,  H01L21/76224

Abstract: In a general aspect, a semiconductor device assembly includes a first portion of a semiconductor substrate; a second portion of the semiconductor substrate, and a semiconductor device layer disposed on the first portion of the semiconductor substrate and the second portion of the semiconductor substrate. The semiconductor device layer includes a first semiconductor device disposed on the first portion of the semiconductor substrate, and a second semiconductor device disposed on the second portion of the semiconductor substrate. The assembly also includes an isolation trench defined in the semiconductor substrate that has a dielectric material disposed therein. The isolation trench is disposed between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate, and electrically isolates the first portion of the semiconductor substrate from the second portion of the semiconductor substrate. The semiconductor device layer excludes the isolation trench.

公开(公告)号：US20200083361A1

公开(公告)日：2020-03-12

申请号：US16123115

申请日：2018-09-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Peter MOENS ,  Abhishek BANERJEE ,  Piet VANMEERBEEK

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06 ,  H01L27/07 ,  H01L29/47 ,  H01L29/66

Abstract: An electronic device can include a drain electrode of a high electron mobility transistor overlying a channel layer; a source electrode overlying the channel layer, wherein a lowermost portion of the source electrode overlies at least a portion of the channel layer; and a gate electrode of the high electron mobility transistor overlying the channel layer; and a current limiting control structure that controls current passing between the drain and source electrodes. The current limiting control structure can be disposed between the source and gate electrodes, the current limiting control structure can be coupled to the source electrode and the first high electron mobility transistor, and the current limiting control structure has a threshold voltage. The current limiting control structure can be a Schottky-gated HEMT or a MISHEMT.

公开(公告)号：US20160322485A1

公开(公告)日：2016-11-03

申请号：US15133657

申请日：2016-04-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Balaji PADMANABHAN ,  Prasad VENKATRAMAN ,  Chun-Li LIU ,  Peter MOENS

IPC: H01L29/747 ,  H01L23/495 ,  H01L29/74 ,  H01L27/088 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/747 ,  H01L21/8258 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/40 ,  H01L25/115 ,  H01L25/18 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0883 ,  H01L29/205 ,  H01L29/404 ,  H01L29/4238 ,  H01L29/7416 ,  H01L29/742 ,  H01L29/7786 ,  H01L29/7787 ,  H01L2224/0603 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/00014 ,  H03K17/6874 ,  H03K2017/6878 ,  H03K2217/0009 ,  H03K2217/0018 ,  H01L2224/37099

Abstract: An electronic device can include a bidirectional HEMT. In an aspect, a packaged electronic device can include the bidirectional HEMT can be part of a die having a die substrate connection that is configured to be at a fixed voltage, electrically connected to drain/source or source/drain depending on current flow through the bidirectional HEMT, or electrically float. In another aspect, the electronic device can include Kelvin connections on both the drain/source and source/drain side of the circuit. In a further embodiment, a circuit can include the bidirectional HEMT, switch transistors, and diodes with breakdown voltages to limit voltage swings at the drain/source and source/drain of the switch transistors.

Abstract translation: 电子设备可以包括双向HEMT。 一方面，封装的电子设备可以包括双向HEMT可以是具有被配置为处于固定电压的管芯衬底连接的管芯的一部分，其电连接到漏极/源极或源极/漏极，这取决于通过 双向HEMT或电浮动。 在另一方面，电子设备可以在电路的漏极/源极和源极/漏极侧上包括开尔文连接。 在另一实施例中，电路可以包括双向HEMT，开关晶体管和具有击穿电压的二极管，以限制开关晶体管的漏极/源极和源极/漏极处的电压摆幅。

公开(公告)号：US20160148997A1

公开(公告)日：2016-05-26

申请号：US15009380

申请日：2016-01-28

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Peter MOENS ,  Ana VILLAMOR ,  Piet VANMEERBEEK ,  Jaume ROIG-GUITART ,  Filip BOGMAN

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L21/76 ,  H01L21/265

CPC classification number: H01L29/0634 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/76 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

Abstract: In one embodiment, a semiconductor substrate is provided having a localized superjunction structure extending from a major surface. A doped region is then formed adjacent the localized superjunction structure to create a charge imbalance therein. In one embodiment, the doped region can be an ion implanted region formed within the localized superjunction structure. In another embodiment, the doped region can be an epitaxial layer having a graded dopant profile adjoining the localized superjunction structure. The charge imbalance can improve, among other things, unclamped inductive switching (UIS) performance.

Abstract translation: 在一个实施例中，提供了具有从主表面延伸的局部超连接结构的半导体衬底。 然后在局部超结结构附近形成掺杂区，以在其中产生电荷不平衡。 在一个实施例中，掺杂区域可以是形成在局部超结结构内的离子注入区域。 在另一个实施例中，掺杂区域可以是具有与局部超结构结构相邻的分级掺杂剂分布的外延层。 电荷不平衡可以改善，尤其是松开感应开关（UIS）性能。

公开(公告)号：US20160099319A1

公开(公告)日：2016-04-07

申请号：US14966649

申请日：2015-12-11

Applicant: Semiconductor Components Industries, LLC

Inventor： Hocine Bouzid ZIAD ,  Peter MOENS ,  Eddy DE BACKER

IPC: H01L29/205 ,  H01L29/06 ,  H01L29/778 ,  H01L29/16

CPC classification number: H01L29/205 ,  H01L21/02021 ,  H01L21/02087 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02595 ,  H01L21/02598 ,  H01L21/02639 ,  H01L23/562 ,  H01L29/0692 ,  H01L29/1604 ,  H01L29/2003 ,  H01L29/513 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer can include a substrate, a poly template layer, and a semiconductor layer. The substrate has a central region and an edge region, the poly template layer is disposed along a peripheral edge of the substrate, and a semiconductor layer over the central region, wherein the semiconductor layer is monocrystalline. In an embodiment, the poly template layer and the monocrystalline layer are laterally spaced apart from each other by an intermediate region. In another embodiment, the semiconductor layer can include aluminum. A process of forming the substrate can include forming a patterned poly template layer within the edge region and forming a semiconductor layer over the primary surface. Another process of forming the substrate can include forming a semiconductor layer over the primary surface and removing a portion of the semiconductor layer so that the semiconductor layer is spaced apart from an edge of the substrate.

Abstract translation: 半导体晶片可以包括基板，多晶模板层和半导体层。 衬底具有中心区域和边缘区域，多晶模板层沿着衬底的周缘设置，并且在中心区域上形成半导体层，其中半导体层是单晶的。 在一个实施方案中，多晶型层和单晶层通过中间区域彼此横向间隔开。 在另一个实施例中，半导体层可以包括铝。 形成衬底的工艺可以包括在边缘区域内形成图案化的多晶模板层，并在主表面上形成半导体层。 形成衬底的另一工艺可以包括在主表面上形成半导体层，并且去除半导体层的一部分，使得半导体层与衬底的边缘间隔开。

公开(公告)号：US20150295025A1

公开(公告)日：2015-10-15

申请号：US14249677

申请日：2014-04-10

Applicant: Semiconductor Components Industries, LLC

Inventor： Jaume ROIG GUITART ,  Zia HOSSAIN ,  Peter MOENS

IPC: H01L29/06 ,  H01L29/40

CPC classification number: H01L29/0634 ,  H01L29/06 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/36 ,  H01L29/40 ,  H01L29/402 ,  H01L29/7811 ,  H01L29/7813

Abstract: An electronic device can include an electronic component and a termination region adjacent to the electronic component region. In an embodiment, the termination region can include an insulating region that extends a depth into a semiconductor layer, wherein the depth is less than 50% of the thickness of the semiconductor layer. In another embodiment, the termination region can include a first insulating region that extends a first depth into the semiconductor layer, and a second insulating region that extends a second depth into the semiconductor layer, wherein the second depth is less than the first depth. In another aspect, a process of forming an electronic device can include patterning a semiconductor layer to define a trench within termination region while another trench is being formed for an electronic component within an electronic component region.

Abstract translation: 电子设备可以包括电子部件和与电子部件区域相邻的端接区域。 在一个实施例中，终端区域可以包括将深度延伸到半导体层中的绝缘区域，其中深度小于半导体层厚度的50％。 在另一个实施例中，终端区域可以包括将第一深度延伸到半导体层中的第一绝缘区域和将第二深度延伸到半导体层中的第二绝缘区域，其中第二深度小于第一深度。 在另一方面，形成电子器件的工艺可以包括图案化半导体层以限定终止区域内的沟槽，同时为电子部件区域内的电子部件形成另一沟槽。

公开(公告)号：US20140264454A1

公开(公告)日：2014-09-18

申请号：US14191030

申请日：2014-02-26

Applicant: Semiconductor Components Industries, LLC

Inventor： Abhishek BANERJEE ,  Peter MOENS

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462

Abstract: In one embodiment, a high electron mobility device structure includes heterostructure with a Group III-nitride channel layer and a Group III-nitride barrier layer that forms a two-dimensional electron gas layer at an interface between the two layers. At least one current carrying electrode includes a recess-structured conductive contact adjoining and making Ohmic contact with the two-dimensional electron gas layer. The recess-structured conductive contact has at least one side surface defined to have a rounded wavy shape.

Abstract translation: 在一个实施例中，高电子迁移率器件结构包括具有III族氮化物沟道层的异质结构和在两层之间的界面处形成二维电子气体层的III族氮化物势垒层。 至少一个载流电极包括邻接并与二维电子气体层进行欧姆接触的凹陷结构的导电接触。 凹陷结构的导电接触件具有限定为具有圆形波状形状的至少一个侧表面。

公开(公告)号：US20140264367A1

公开(公告)日：2014-09-18

申请号：US14190839

申请日：2014-02-26

Applicant: Semiconductor Components Industries, LLC

Inventor： Abhishek BANERJEE ,  Peter MOENS

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/66431 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/4236 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: A HEMT semiconductor device can include a dielectric layer that includes a silicon nitride film and an AlN film. In an embodiment, the HEMT semiconductor device can include a GaN film and an AlGaN film. In a process of forming the HEMT device, the AlN can provide an etch stop when forming an opening for a gate electrode.

Abstract translation: HEMT半导体器件可以包括包含氮化硅膜和AlN膜的电介质层。 在一个实施例中，HEMT半导体器件可以包括GaN膜和AlGaN膜。 在形成HEMT器件的过程中，当形成栅电极的开口时，AlN可以提供蚀刻停止。

公开(公告)号：US20220262940A1

公开(公告)日：2022-08-18

申请号：US17248989

申请日：2021-02-16

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Peter COPPENS ,  Peter MOENS ,  Joris BAELE

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66

Abstract: A High Electron Mobility Transistor (HEMT) includes a source, a drain, a channel layer extending between the source and the drain, a barrier layer formed in contact with the channel layer, and extending between the source and the drain, and a gate formed in contact with, and covering at least a portion of, the barrier layer. The gate has gate edge portions and a gate central portion, and dielectric spacers may be formed over the gate edge portions, with the dielectric spacers having a first width therebetween proximal to the gate, and a second width therebetween distal from the gate, where the second width is longer than the first width.

公开(公告)号：US20220216332A1

公开(公告)日：2022-07-07

申请号：US17143301

申请日：2021-01-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Abhishek BANERJEE ,  Peter MOENS ,  Herbert DE VLEESCHOUWER ,  Peter COPPENS

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/20

Abstract: High Electron Mobility Transistors (HEMTs) are described with a circular gate, with a drain region disposed within the circular gates and circular source region disposed around the circular gates. The circular gate and the circular source region may form complete circles.