公开(公告)号：US20210320212A1

公开(公告)日：2021-10-14

申请号：US17358295

申请日：2021-06-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Tetsuhiro TANAKA ,  Hirokazu WATANABE ,  Yuhei SATO ,  Yasumasa YAMANE ,  Daisuke MATSUBAYASHI

IPC: H01L29/786 ,  H01L29/45 ,  H01L29/66

Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.

公开(公告)号：US20200279851A1

公开(公告)日：2020-09-03

申请号：US16645665

申请日：2018-09-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Hideomi SUZAWA

IPC: H01L27/105 ,  H01L29/786 ,  H01L23/528 ,  H01L27/02 ,  H01L29/24 ,  H01L29/66

Abstract: A semiconductor device that can be highly integrated is provided. The semiconductor device includes a first transistor, a second transistor, and an electrode. The first transistor and the second transistor include an oxide, a gate insulator over the oxide, and a gate. The electrode is connected to one of a source and a drain of the first transistor and one of a source and a drain of the second transistor. The channel length of the first transistor is longer than the short side of the first conductor. The channel length of the second transistor is longer than the short side of the second conductor.

公开(公告)号：US20180190828A1

公开(公告)日：2018-07-05

申请号：US15908851

申请日：2018-03-01

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA

IPC: H01L29/786 ,  H01L27/06 ,  H01L27/1156 ,  H01L27/12 ,  H01L29/16 ,  H01L29/78 ,  H01L29/06 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/0657 ,  H01L29/16 ,  H01L29/24 ,  H01L29/78

Abstract: Provided is a highly integrated semiconductor device, a semiconductor device with large storage capacity with respect to an area occupied by a capacitor, a semiconductor device capable of high-speed writing, a semiconductor device capable of high-speed reading, a semiconductor device with low power consumption, or a highly reliable semiconductor device. The semiconductor device includes a first transistor, a second transistor, and a capacitor. A conductor penetrates and connects the first transistor, the capacitor, and the second transistor. An insulator is provided on a side surface of the conductor that penetrates the capacitor.

公开(公告)号：US20170033230A1

公开(公告)日：2017-02-02

申请号：US15292287

申请日：2016-10-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tetsuhiro TANAKA ,  Hideomi SUZAWA ,  Yasumasa YAMANE ,  Yuhei SATO ,  Sachiaki TEZUKA

IPC: H01L29/786 ,  H01L27/12 ,  H01L27/06

CPC classification number: H01L29/7869 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1225 ,  H01L29/16

Abstract: To provide a transistor with stable electrical characteristics, a transistor with a low off-state current, a transistor with a high on-state current, a semiconductor device including the transistor, or a durable semiconductor device. The semiconductor device includes a first transistor using silicon, an aluminum oxide film over the first transistor, and a second transistor using an oxide semiconductor over the aluminum oxide film. The oxide semiconductor has a lower hydrogen concentration than silicon.

Abstract translation: 为了提供具有稳定电特性的晶体管，具有低截止电流的晶体管，具有高导通电流的晶体管，包括晶体管的半导体器件或耐用的半导体器件。 半导体器件包括使用硅的第一晶体管，在第一晶体管上的氧化铝膜，以及在氧化铝膜上使用氧化物半导体的第二晶体管。 氧化物半导体的氢浓度低于硅。

公开(公告)号：US20160056272A1

公开(公告)日：2016-02-25

申请号：US14885545

申请日：2015-10-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masayuki SAKAKURA ,  Hideomi SUZAWA ,  Kazuya HANAOKA

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L29/78696 ,  H01L29/045 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869

Abstract: To provide a semiconductor device having a structure capable of suppressing deterioration of its electrical characteristics which becomes apparent with miniaturization. The semiconductor device includes a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a source electrode and a drain electrode in contact with the second oxide semiconductor film; a third oxide semiconductor film over the second oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film over the third oxide semiconductor film; and a gate electrode over the gate insulating film. A first interface between the gate electrode and the gate insulating film has a region closer to the insulating surface than a second interface between the first oxide semiconductor film and the second oxide semiconductor film.

Abstract translation: 提供具有能够抑制其电特性劣化的结构的半导体器件，其在小型化时变得明显。 半导体器件包括绝缘表面上的第一氧化物半导体膜; 第一氧化物半导体膜上的第二氧化物半导体膜; 与第二氧化物半导体膜接触的源电极和漏电极; 第二氧化物半导体膜上的第三氧化物半导体膜，源电极和漏电极; 第三氧化物半导体膜上的栅极绝缘膜; 以及栅极绝缘膜上的栅电极。 栅电极和栅绝缘膜之间的第一界面具有比第一氧化物半导体膜和第二氧化物半导体膜之间的第二界面更接近绝缘表面的区域。

公开(公告)号：US20150280003A1

公开(公告)日：2015-10-01

申请号：US14722260

申请日：2015-05-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA

IPC: H01L29/786 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/7869 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78648

Abstract: A transistor that is to be provided has such a structure that a source electrode layer and a drain electrode layer between which a channel formation region is sandwiched has regions projecting in a channel length direction at lower end portions, and an insulating layer is provided, in addition to a gate insulating layer, between the source and drain electrode layers and a gate electrode layer. In the transistor, the width of the source and drain electrode layers is smaller than that of an oxide semiconductor layer in the channel width direction, so that an area where the gate electrode layer overlaps with the source and drain electrode layers can be made small. Further, the source and drain electrode layers have regions projecting in the channel length direction at lower end portions.

Abstract translation: 要提供的晶体管具有这样的结构，其中夹在沟道形成区域之间的源电极层和漏电极层具有在下端部沿沟道长度方向突出的区域，并且设置有绝缘层， 添加到栅极绝缘层之间，在源极和漏极电极层之间以及栅极电极层。 在晶体管中，源极和漏极电极层的宽度小于沟道宽度方向上的氧化物半导体层的宽度，从而可以使栅电极层与源极和漏极电极层重叠的区域变小。 此外，源极和漏极电极层具有在下端部沿沟道长度方向突出的区域。

公开(公告)号：US20150137132A1

公开(公告)日：2015-05-21

申请号：US14589369

申请日：2015-01-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Koji ONO ,  Hideomi SUZAWA ,  Tatsuya ARAO

IPC: H01L27/12

CPC classification number: H01L27/1222 ,  G02F1/13624 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/127 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L33/08 ,  H01L33/62 ,  H01L2029/7863 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is an electroluminescence device having a substrate, a thin film transistor over the substrate, an insulating film over the thin film transistor, an electroluminescence element over the insulating film, a passivation film over the electroluminescence element, and a counter substrate over the passivation film. The electroluminescence element is configured to emit light through the counter substrate, and a space between the substrate and the counter substrate is filled with a filler. The electroluminescence device is featured by the tapered side surface of a gate electrode of the thin film transistor.

Abstract translation: 公开了一种电致发光器件，其具有衬底，衬底上的薄膜晶体管，薄膜晶体管上的绝缘膜，绝缘膜上的电致发光元件，电致发光元件上的钝化膜以及钝化膜上的对置衬底 。 电致发光元件被配置为通过对置基板发光，并且用填充物填充基板和对向基板之间的空间。 电致发光元件的特征在于薄膜晶体管的栅电极的锥形侧面。

公开(公告)号：US20150079730A1

公开(公告)日：2015-03-19

申请号：US14548955

申请日：2014-11-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA

IPC: H01L21/465 ,  H01L29/66

CPC classification number: H01L27/127 ,  G02F1/134309 ,  G02F1/136227 ,  G02F1/167 ,  G09F21/04 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0809 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28 ,  H01L21/465 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3262 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.

Abstract translation: 本发明的目的是建立一种其中使用氧化物半导体的半导体器件的制造中的加工技术。 在基板上形成栅电极，在栅电极上形成栅极绝缘层，在栅极绝缘层上形成氧化物半导体层，通过湿蚀刻加工氧化物半导体层，形成岛状氧化物半导体层 形成导电层以覆盖岛状氧化物半导体层，通过干蚀刻处理导电层以形成源电极，并且通过干蚀刻除去漏电极和岛状氧化物半导体层的一部分， 在岛状氧化物半导体层中形成凹部。

公开(公告)号：US20140332801A1

公开(公告)日：2014-11-13

申请号：US14337583

申请日：2014-07-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Hideomi SUZAWA

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/10 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L27/1156 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/66477 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/78606 ,  H01L29/78636 ,  H01L29/78696

Abstract: A bottom-gate transistor with a short channel length and a method for manufacturing the transistor are provided. A bottom-gate transistor with a short channel length in which portions of a source electrode and a drain electrode which are proximate to a channel formation region are thinner than other portions thereof was devised. In addition, the portions of the source electrode and the drain electrode which are proximate to the channel formation region are formed in a later step than the other portions thereof, whereby a bottom-gate transistor with a short channel length can be manufactured.

Abstract translation: 提供具有短沟道长度的底栅晶体管和制造晶体管的方法。 设计了具有短沟道长度的底栅晶体管，其中靠近沟道形成区的源电极和漏电极的部分比其它部分薄。 此外，靠近沟道形成区域的源电极和漏极的部分以比其它部分稍后的步骤形成，由此可以制造具有短沟道长度的底栅晶体管。

公开(公告)号：US20140273343A1

公开(公告)日：2014-09-18

申请号：US14287494

申请日：2014-05-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunichi ITO ,  Miyuki HOSOBA ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA

IPC: H01L29/66

CPC classification number: H01L29/66969 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/7869

Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks. In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by dry etching in which an etching gas is used, and a second etching step is performed by wet etching in which an etchant is used.

Abstract translation: 目的是以低成本，高生产率制造包括氧化物半导体的半导体器件，使得通过减少曝光掩模的数量来简化光刻工艺。 在制造包括通道蚀刻反交错薄膜晶体管的半导体器件的方法中，使用使用作为曝光的多色调掩模形成的掩模层来蚀刻氧化物半导体膜和导电膜 光透过该掩模以具有多个强度。 在蚀刻步骤中，通过使用蚀刻气体的干蚀刻进行第一蚀刻步骤，并且通过使用蚀刻剂的湿蚀刻进行第二蚀刻步骤。