公开(公告)号：US09087780B2

公开(公告)日：2015-07-21

申请号：US13872468

申请日：2013-04-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wan-Ting Chen ,  Mu-Hsuan Chan ,  Yi-Chian Liao ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L23/48 ,  H01L23/28 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/561 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L23/28 ,  H01L23/31 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5384 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10253 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/81

Abstract: A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element.

Abstract translation: 提供半导体封装，包括：载体; 至少设置在所述载体上的插入件; 形成在所述载体上的密封剂，用于在暴露所述插入件的顶侧的同时封装所述插入件; 设置在所述插入件的顶侧的半导体元件; 以及形成在插入件和半导体元件之间的粘合剂。 通过用封装剂封装插入件，避免了插入器的翘曲，并且为了将半导体元件设置在其上提供平坦的表面，从而提高了插入件与半导体元件之间的电连接的可靠性。

公开(公告)号：US20150155258A1

公开(公告)日：2015-06-04

申请号：US14616078

申请日：2015-02-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Feng Chan ,  Mu-Hsuan Chan ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/81 ,  H01L21/441 ,  H01L21/56 ,  H01L23/145 ,  H01L23/147 ,  H01L23/488 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/13084 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.

Abstract translation: 用于形成在具有多个接合焊盘的基板上的导电凸块结构。 导电凸块结构包括在接合焊盘上形成的第一金属层，形成在第一金属层上的第二金属层和形成在第二金属层上的第三金属层。 第二金属层的第二熔点高于第三金属层的第三熔点。 因此，首先对第三金属层进行热压接，从而将基板粘合到另一基板上，然后进行回流处理，使第二金属层和第三金属层彼此熔融 从而形成合金部分，从而避免基板的开裂。

公开(公告)号：US08895367B2

公开(公告)日：2014-11-25

申请号：US13964465

申请日：2013-08-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Jung-Pang Huang ,  Hui-Min Huang ,  Kuan-Wei Chuang ,  Chun-Tang Lin ,  Yih-Jenn Jiang

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/36 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/014 ,  H01L2924/3511

Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.

Abstract translation: 半导体封装包括：具有多个电极焊盘的有源表面和与该有源表面相对的无效表面的芯片; 密封剂，其封装所述芯片并且具有相对的第一和第二表面，所述第一表面与所述芯片的有源表面齐平; 以及形成在密封剂的第二表面上的第一和第二金属层，由此为整个结构提供刚性支撑以防止翘曲并促进整体结构的散热。

公开(公告)号：US20140127838A1

公开(公告)日：2014-05-08

申请号：US13845698

申请日：2013-03-18

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Pin-Cheng Huang ,  Chun-Tang Lin ,  Wen-Tsung Tseng ,  Yi-Che Lai

IPC: H01L21/66

CPC classification number: H01L22/14 ,  H01L21/6836 ,  H01L22/20 ,  H01L23/147 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2221/68331 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/16195 ,  H01L2924/351 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/81

Abstract: A method of testing a semiconductor package is provided, including: disposing at least an interposer on a top surface of an adhesive layer, the interposer having a first surface and a second surface opposite to the first surface, a plurality of conductive elements disposed between the second surface of the interposer and the adhesive layer; disposing at least a semiconductor chip on the first surface of the interposer, and performing an electrical test on the semiconductor chip via the conductive elements, wherein if there are a plurality of semiconductor chips that are disposed on the first surface of the interposer, the step of disposing the semiconductor chip and performing the electrical test on the semiconductor chip is iterated; and removing the adhesive layer. By using the method, the fabrication cost and equipment cost of the semiconductor package are reduced, and product yield is increased.

Abstract translation: 提供了一种测试半导体封装的方法，包括：至少在粘合剂层的顶表面上设置插入件，所述插入件具有第一表面和与第一表面相对的第二表面，多个导电元件设置在第二表面之间 插入器的第二表面和粘合剂层; 在所述插入件的第一表面上设置至少一个半导体芯片，并且经由所述导电元件对所述半导体芯片进行电测试，其中如果存在设置在所述插入件的第一表面上的多个半导体芯片，则所述步骤 重复设置半导体芯片并对半导体芯片进行电气测试; 并去除粘合剂层。 通过使用该方法，半导体封装的制造成本和设备成本降低，产品产量增加。

公开(公告)号：US11532495B2

公开(公告)日：2022-12-20

申请号：US17073783

申请日：2020-10-19

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Wu-Hung Yen ,  Yi-Hsien Huang ,  Chun-Tang Lin ,  Shu-Hua Chen ,  Shou-Qi Chang

IPC: H01L21/67

Abstract: A chip matching system and a corresponding method are provided. The method defines a plurality of first electronic components in a first wafer as various grades of chips and defines a plurality of second electronic components in a second wafer as various grades of chips, and then grades of the first electronic components and the second electronic components are matched to generate target information, and finally the first and second electronic components are integrated in the same position according to the target information. Therefore, the highest-grade chips can be arranged in a multi-chip module to optimize the quality of the multi-chip module.

公开(公告)号：US20220068680A1

公开(公告)日：2022-03-03

申请号：US17073783

申请日：2020-10-19

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Wu-Hung Yen ,  Yi-Hsien Huang ,  Chun-Tang Lin ,  Shu-Hua Chen ,  Shou-Qi Chang

IPC: H01L21/67

Abstract: A chip matching system and a corresponding method are provided. The method defines a plurality of first electronic components in a first wafer as various grades of chips and defines a plurality of second electronic components in a second wafer as various grades of chips, and then grades of the first electronic components and the second electronic components are matched to generate target information, and finally the first and second electronic components are integrated in the same position according to the target information. Therefore, the highest-grade chips can be arranged in a multi-chip module to optimize the quality of the multi-chip module.

公开(公告)号：US11056442B2

公开(公告)日：2021-07-06

申请号：US15624590

申请日：2017-06-15

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Po-Hao Wang ,  Chun-Tang Lin ,  Shou-Qi Chang ,  Yu-Hsiang Hsieh

IPC: H01L23/00 ,  H01L23/14 ,  H01L25/065 ,  H01L23/498 ,  H01L23/13 ,  H01L23/31

Abstract: A substrate structure has an obtuse portion formed between a side surface and a bottom surface of a substrate body. The obtuse portion includes a plurality of turning surfaces to disperse the stress of the substrate body generated in the packaging process. Therefore, the substrate body is prevented from being cracked. A method for fabricating the substrate structure and an electronic package including the substrate structure are also provided.

公开(公告)号：US20200350261A1

公开(公告)日：2020-11-05

申请号：US16875240

申请日：2020-05-15

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Po-Hao Wang ,  Chang-Fu Lin ,  Chun-Tang Lin ,  Bo-Hao Chang

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: Provided is a substrate structure, including a substrate having at least one chamfer formed on a surface thereof, and a plurality of conductive bodies formed to the substrate. Therefore, a stress generated during the packaging process is alleviated through the chamfer, and the substrate structure is prevented from being cracked. An electronic package employing the substrate structure is also provided.

公开(公告)号：US20200091059A1

公开(公告)日：2020-03-19

申请号：US16690801

申请日：2019-11-21

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Chun-Tang Lin ,  Fu-Tang Huang

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.

公开(公告)号：US10522453B2

公开(公告)日：2019-12-31

申请号：US15352856

申请日：2016-11-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Chun-Tang Lin ,  Fu-Tang Huang

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.