公开(公告)号：US20170125324A1

公开(公告)日：2017-05-04

申请号：US14932055

申请日：2015-11-04

Applicant: Texas Instruments Incorporated

Inventor： Rajeev D. Joshi ,  Hau Nguyen ,  Anindya Poddar ,  Ken Pham

IPC: H01L23/495 ,  H01L25/16 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49537 ,  H01L21/4825 ,  H01L21/4828 ,  H01L23/3121 ,  H01L23/49544 ,  H01L23/49558 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49589 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L25/16 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/40245 ,  H01L2224/83815 ,  H01L2224/83851 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A dual leadframe (100) for semiconductor systems comprising a first leadframe (110) having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe (120) having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions (150) in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material (140) filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.

公开(公告)号：US20240363465A1

公开(公告)日：2024-10-31

申请号：US18309546

申请日：2023-04-28

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Daiki Komatsu ,  Hau Nguyen

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/3135 ,  H01L21/561 ,  H01L21/78 ,  H01L23/49513 ,  H01L24/05 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L21/568 ,  H01L23/291 ,  H01L23/293 ,  H01L2224/05558 ,  H01L2224/05686 ,  H01L2224/0569 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48245 ,  H01L2224/49173 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/05442 ,  H01L2924/0695 ,  H01L2924/07025

Abstract: An electronic device includes a semiconductor die, a die attach pad, an adhesive, a conductive lead, and a package structure, where the semiconductor die has opposite first and second sides, a conductive terminal on the second side, and an electrical isolation coating layer that extends on the first side, the adhesive adheres the first side of the semiconductor die to the die attach pad, the conductive lead is electrically coupled to the conductive terminal of the semiconductor die, and the package structure encloses at least a portion of the semiconductor die.

公开(公告)号：US11955456B2

公开(公告)日：2024-04-09

申请号：US17364735

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Ashok Surendra Prabhu ,  Hau Nguyen ,  Kurt Edward Sincerbox ,  Makoto Shibuya

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/94 ,  H01L21/4825 ,  H01L21/4839 ,  H01L21/563 ,  H01L23/3157 ,  H01L23/367 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/16 ,  H01L25/0655 ,  H01L24/97 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2924/182

Abstract: In a described example, an apparatus includes: a first package substrate having a die mount surface; a semiconductor die flip chip mounted to the first package substrate on the die mount surface, the semiconductor die having post connects having proximate ends on bond pads on an active surface of the semiconductor die, and extending to distal ends away from the semiconductor die having solder bumps, wherein the solder bumps form solder joints to the package substrate; a second package substrate having a thermal pad positioned with the thermal pad over a backside surface of the semiconductor die, the thermal pad comprising a thermally conductive material; and a mold compound covering a portion of the first package substrate, a portion of the second package substrate, the semiconductor die, and the post connects, thermal pad having a surface exposed from the mold compound.

公开(公告)号：US20230317568A1

公开(公告)日：2023-10-05

申请号：US17710077

申请日：2022-03-31

Applicant: Texas Instruments Incorporated

Inventor： Daiki Komatsu ,  Anindya Poddar ,  Hau Nguyen

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/49513 ,  H01L24/32 ,  H01L23/3107 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L21/56 ,  H01L21/78 ,  H01L2224/32245 ,  H01L2224/2919 ,  H01L2224/48221 ,  H01L2224/73265 ,  H01L2224/92247

Abstract: An integrated circuit package includes a die attach pad (DAP) having a top surface and a layer of insulating material applied to the top surface of the DAP. A silicon-on-insulator (SOI) device is mounted on the insulating material using a die attach paste or film. A plurality of leads are coupled to the SOI device using bond wires. A mold compound covers at least a portion of the DAP and the SOI device. The insulating material may be polyimide or polyamide-imide that has been inkjet printed or screen printed on the DAP. The insulating material may be a parylene material that is applied to the top surface of the DAP using chemical vapor deposition. The insulating material has a thickness of 1-25 um and has a breakdown voltage of approximately 250V/um.

公开(公告)号：US11450638B2

公开(公告)日：2022-09-20

申请号：US17009648

申请日：2020-09-01

Applicant: Texas Instruments Incorporated

Inventor： Dibyajat Mishra ,  Ashok Prabhu ,  Tomoko Noguchi ,  Luu Thanh Nguyen ,  Anindya Poddar ,  Makoto Yoshino ,  Hau Nguyen

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/31

Abstract: A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.

公开(公告)号：US10763231B2

公开(公告)日：2020-09-01

申请号：US16047888

申请日：2018-07-27

Applicant: Texas Instruments Incorporated

Inventor： Dibyajat Mishra ,  Ashok Prabhu ,  Tomoko Noguchi ,  Luu Thanh Nguyen ,  Anindya Poddar ,  Makoto Yoshino ,  Hau Nguyen

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495

Abstract: A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.

公开(公告)号：US10573582B2

公开(公告)日：2020-02-25

申请号：US16378171

申请日：2019-04-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajeev D. Joshi ,  Hau Nguyen ,  Anindya Poddar ,  Ken Pham

IPC: H01L23/495 ,  H01L21/48 ,  H01L25/16 ,  H01L23/00 ,  H01L23/31

Abstract: A dual leadframe (100) for semiconductor systems comprising a first leadframe (110) having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe (120) having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions (150) in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material (140) filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.

公开(公告)号：US09663357B2

公开(公告)日：2017-05-30

申请号：US14963362

申请日：2015-12-09

Applicant: Texas Instruments Incorporated

Inventor： Jie Mao ,  Hau Nguyen ,  Luu Nguyen ,  Anindya Poddar

IPC: H01L21/683 ,  B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00873 ,  B81B7/007 ,  B81B2201/0214 ,  B81B2201/0235 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0278 ,  B81B2201/0292 ,  B81B2201/047 ,  B81B2207/07 ,  B81B2207/098 ,  B81C1/00333 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0159 ,  B81C2201/0181 ,  B81C2201/0188 ,  B81C2203/0136 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3121 ,  H01L24/19 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/96 ,  H01L2924/3511

Abstract: A method for fabricating packaged semiconductor devices (100) with an open cavity (110a) in panel format; placing (process 201) on an adhesive carrier tape a panel-sized grid of metallic pieces having a flat pad (230) and symmetrically placed vertical pillars (231); attaching (process 202) semiconductor chips (101) with sensor systems face-down onto the tape; laminating (process 203) and thinning (process 204) low CTE insulating material (234) to fill gaps between chips and grid; turning over (process 205) assembly to remove tape; plasma-cleaning assembly front side, sputtering and patterning (process 206) uniform metal layer across assembly and optionally plating (process 209) metal layer to form rerouting traces and extended contact pads for assembly; laminating (process 212) insulating stiffener across panel; opening (process 213) cavities in stiffener to access the sensor system; and singulating (process 214) packaged devices by cutting metallic pieces.