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公开(公告)号：US10353285B2
公开(公告)日：2019-07-16
申请号：US16010118
申请日：2018-06-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsin-Chang Lee , Pei-Cheng Hsu , Yun-Yue Lin , Hsuan-Chen Chen , Hsuan-I Wang , Anthony Yen
Abstract: A structure including an EUV mask and a pellicle attached to the EUV mask. The pellicle includes a pellicle frame and a plurality of pellicle membrane layers attached to the pellicle frame. The plurality of pellicle membrane layers include at least one core pellicle membrane layer and an additional pellicle membrane layer is disposed on the at least one core pellicle membrane layer. In some embodiments, the additional pellicle membrane layer is a material having a thermal emissivity greater than 0.2, a transmittance greater than 80%, and a refractive index (n) for 13.5 nanometer source of greater than 0.9.
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公开(公告)号：US10162258B2
公开(公告)日：2018-12-25
申请号：US15381033
申请日：2016-12-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yun-Yue Lin , Hsuan-Chen Chen , Chih-Cheng Lin , Hsin-Chang Lee , Yao-Ching Ku , Wei-Jen Lo , Anthony Yen , Chin-Hsiang Lin , Mark Chien
Abstract: A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. In some examples, after forming the graphene layer, the first dielectric layer is patterned to form an opening in the first dielectric layer that exposes a portion of the back surface of the substrate. Thereafter, while using the patterned first dielectric layer as a mask, an etching process may be performed to the back surface of the substrate to form a pellicle having a pellicle membrane that includes the graphene layer.
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公开(公告)号：US09870612B2
公开(公告)日：2018-01-16
申请号：US15254607
申请日：2016-09-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shinn-Sheng Yu , Anthony Yen , Wen-Chuan Wang , Sheng-Chi Chin
CPC classification number: G06T7/0004 , G03F1/24 , G03F1/26 , G03F1/72 , G03F1/84 , G06T7/001 , G06T7/0081 , G06T7/11 , G06T2207/10004 , G06T2207/10056 , G06T2207/30148 , H01L21/0273
Abstract: A method includes inspecting a mask to locate a defect region for a defect of the mask. A phase distribution of an aerial image of the defect region is acquired. A point spread function of an imaging system is determined. One or more repair regions of the mask are identified based on the phase distribution of the aerial image of the defect region and the point spread function. A repair process is performed to the one or more repair regions of the mask to form one or more repair features.
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公开(公告)号：US09360749B2
公开(公告)日：2016-06-07
申请号：US14260651
申请日：2014-04-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
Inventor： Yun-Yue Lin , Chia-Jen Chen , Hsin-Chang Lee , Anthony Yen
Abstract: A pellicle structure, a pellicle-mask structure, and a method for forming the pellicle structure are provided. The pellicle structure includes a pellicle film made of a carbon-based material. In addition, the pellicle film is configured to protect a mask structure in a lithography process. The pellicle-mask structure includes a mask substrate having a mask pattern formed over the mask substrate and the pellicle frame disposed on the mask substrate. The pellicle-mask structure further includes the pellicle film disposed on the pellicle frame.
Abstract translation: 提供防护薄膜组件，防护薄膜组件，以及防护薄膜组件的形成方法。 防护薄膜组件包括由碳基材料制成的防护薄膜。 此外，防护薄膜被配置为在光刻工艺中保护掩模结构。 防护薄膜组件包括具有形成在掩模基板上的掩模图案和设置在掩模基板上的防护膜框架的掩模基板。 防护薄膜组件还包括设置在防护薄膜组件框架上的防护薄膜。
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25.发明授权Lithography system and method for patterning photoresist layer on EUV mask 有权用于在EUV掩模上图案化光刻胶层的平版印刷系统和方法公开(公告)号：US09341937B2
公开(公告)日：2016-05-17
申请号：US14261809
申请日：2014-04-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yun-Yue Lin , Chia-Jen Chen , Hsin-Chang Lee , Anthony Yen
Abstract: A lithography system for an extreme ultra violet (EUV) mask is provided. The lithography system includes a coupling module. The coupling module includes at least one mask contact element configured to touch a peripheral area of the EUV mask. The lithography system also includes an ammeter having an end electrically connected to the EUV mask through the at least one mask contact element and another end connected to a ground potential. The ammeter includes a sensor configured to measure a current conducting from the EUV mask to the ground potential and a compensation circuit configured to provide a compensation current that is opposite to the current measured by the sensor.
Abstract translation: 提供了用于极紫外（EUV）掩模的光刻系统。 光刻系统包括耦合模块。 耦合模块包括被配置为触摸EUV掩模的外围区域的至少一个掩模接触元件。 光刻系统还包括电流表，其具有通过至少一个掩模接触元件电连接到EUV掩模的端部，另一端连接到接地电位。 电流表包括传感器，其被配置为测量从EUV掩模传导到地电位的电流;以及补偿电路，其被配置为提供与由传感器测量的电流相反的补偿电流。
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Patent Agency Ranking
公开(公告)号：US20150309405A1
公开(公告)日：2015-10-29
申请号：US14259194
申请日：2014-04-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Tsung Shih , Benjamin Lee , Chia-Jen Chen , Shang-Chieh Chien , Shinn-Sheng Yu , Jeng-Horng Chen , Anthony Yen
CPC classification number: G03F1/64 , B29C71/02 , B29C2071/022 , G03F1/62 , G03F7/2002
Abstract: The present disclosure relates to a method of forming an EUV pellicle having an pellicle film connected to a pellicle frame without a supportive mesh, and an associated apparatus. In some embodiments, the method is performed by forming a cleaving plane within a substrate at a position parallel to a top surface of the substrate. A pellicle frame is attached to the top surface of the substrate. The substrate is cleaved along the cleaving plane to form a pellicle film comprising a thinned substrate coupled to the pellicle frame. Prior to cleaving the substrate, the substrate is operated upon to reduce structural damage to the top surface of substrate during formation of the cleaving plane and/or during cleaving the substrate. Reducing structural damage to the top surface of the substrate improves the durability of the thinned substrate and removes a need for a support structure for the pellicle film.
Abstract translation: 本发明涉及一种形成具有连接到没有支撑网的防护薄膜框架的防护薄膜组件的EUV防护薄膜组件的方法，以及相关联的装置。 在一些实施例中，该方法通过在平行于衬底顶表面的位置处在衬底内形成切割平面来进行。 防护薄膜组件框架附接到基板的顶表面。 基底沿着切割平面切割以形成防护薄膜，该薄膜包含连接到防护薄膜框架上的薄化基底。 在切割基板之前，操作基板以在形成切割平面期间和/或在分离基板期间减少对基板顶表面的结构损伤。 降低对基板顶表面的结构损伤提高了薄板基板的耐久性，并且消除了对防护薄膜的支撑结构的需要。
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27.发明授权Extreme ultraviolet (EUV) mask, method of fabricating the EUV mask and method of inspecting the EUV mask 有权极紫外（EUV）掩模，制造EUV掩模的方法和检查EUV掩模的方法公开(公告)号：US09081288B2
公开(公告)日：2015-07-14
申请号：US13955164
申请日：2013-07-31
Applicant: Taiwan Semiconductor Manufacturing Co., LTD.
Inventor： Chih-Tsung Shih , Yen-Cheng Lu , Shinn-Sheng Yu , Jeng-Horng Chen , Anthony Yen
Abstract: An out-of-band (OoB) suppression layer is applied on a reflective multiplayer (ML) coating, so as to avoid the OoB reflection and to enhance the optical contrast at 13.5 nm. A material having a low reflectivity at wavelength of 193-257 nm, for example, silicon carbide (SiC), is used as the OoB suppression layer. A method of fabricating an EUV mask having the OoB suppression layer and a method of inspecting an EUV mask having the OoB suppression are also provided.
Abstract translation: 将带外（OoB）抑制层施加在反射多人（ML）涂层上，以避免OoB反射并增强13.5nm处的光学对比度。 使用波长为193-257nm的低反射率的材料，例如碳化硅（SiC），作为OoB抑制层。 还提供了制造具有OoB抑制层的EUV掩模的方法和检查具有OoB抑制的EUV掩模的方法。
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公开(公告)号：US10955746B2
公开(公告)日：2021-03-23
申请号：US15861156
申请日：2018-01-03
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shinn-Sheng Yu , Ching-Fang Yu , Wen-Chuan Wang , Ting-Hao Hsu , Sheng-Chi Chin , Anthony Yen
Abstract: An extreme ultraviolet lithography method is disclosed. In an example, the EUVL method includes forming a resist layer on a substrate; performing a first exposure process to image a first pattern of a first sub-region of a first mask to the resist layer; performing a second exposure process to image a second pattern of a second sub-region of the first mask to the resist layer; and performing a third exposure process to image a third pattern of a first sub-region of a second mask to the resist layer. The second and third patterns are identical to the first pattern. The first, second and third exposure processes collectively form a latent image of the first pattern on the resist layer.
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公开(公告)号：US10429314B2
公开(公告)日：2019-10-01
申请号：US15883971
申请日：2018-01-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chun-Lin Louis Chang , Shang-Chieh Chien , Shang-Ying Wu , Li-Kai Cheng , Tzung-Chi Fu , Bo-Tsun Liu , Li-Jui Chen , Po-Chung Cheng , Anthony Yen , Chia-Chen Chen
IPC: G01N21/94 , G01N21/88 , G03F7/20 , H01L21/027 , G01N21/956
Abstract: A single-shot metrology for direct inspection of an entirety of the interior of an EUV vessel is provided. An EUV vessel including an inspection tool integrated with the EUV vessel is provided. During an inspection process, the inspection tool is moved into a primary focus region of the EUV vessel. While the inspection tool is disposed at the primary focus region and while providing a substantially uniform and constant light level to an interior of the EUV vessel by way of an illuminator, a panoramic image of an interior of the EUV vessel is captured by way of a single-shot of the inspection tool. Thereafter, a level of tin contamination on a plurality of components of the EUV vessel is quantified based on the panoramic image of the interior of the EUV vessel. The quantified level of contamination is compared to a KPI, and an OCAP may be implemented.
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30.发明申请公开(公告)号：US20190121228A1
公开(公告)日：2019-04-25
申请号：US16220324
申请日：2018-12-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yen-Cheng Lu , Shinn-Sheng Yu , Jeng-Horng Chen , Anthony Yen
Abstract: A lithography system includes a radiation source configured to generate an extreme ultraviolet (EUV) light. The lithography system includes a mask that defines one or more features of an integrated circuit (IC). The lithography system includes an illuminator configured to direct the EUV light onto the mask. The mask diffracts the EUV light into a 0-th order ray and a plurality of higher order rays. The lithography system includes a wafer stage configured to secure a wafer that is to be patterned according to the one or more features defined by the mask. The lithography system includes a pupil phase modulator positioned in a pupil plane that is located between the mask and the wafer stage. The pupil phase modulator is configured to change a phase of the 0-th order ray.
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