公开(公告)号：US20230387082A1

公开(公告)日：2023-11-30

申请号：US18362649

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Sung-Feng Yeh ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L23/31 ,  H01L23/485 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/485 ,  H01L24/08 ,  H01L24/89 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06548 ,  H01L2225/06568

Abstract: A package includes a first device die, and a second device die bonded to the first device die through hybrid bonding. The second device die is larger than the first device die. A first isolation region encapsulates the first device die therein. The first device die, the second device die, and the first isolation region form parts of a first package. A third device die is bonded to the first package through hybrid bonding. The third device die is larger than the first package. A second isolation region encapsulates the first package therein. The first package, the third device die, and the second isolation region form parts of a second package.

公开(公告)号：US20230387000A1

公开(公告)日：2023-11-30

申请号：US18366771

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5283

Abstract: A semiconductor device includes a substrate. A first dielectric layer is over the substrate. A first interconnect is in the first dielectric layer. A second dielectric layer is over the first dielectric layer and the first interconnect. A conductive via extends through the first dielectric layer, the second dielectric layer and the substrate. A topmost surface of the conductive via is level with a topmost surface of the second dielectric layer. A third dielectric layer is over the second dielectric layer and the conductive via. A fourth dielectric layer is over the third dielectric layer. A second interconnect is in the fourth dielectric layer. The second interconnect extends through the third dielectric layer and the second dielectric layer and physically contacts the first interconnect.

公开(公告)号：US20230378015A1

公开(公告)日：2023-11-23

申请号：US18363363

申请日：2023-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Sung-Feng Yeh

IPC: H01L23/36 ,  H01L27/06 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/36 ,  H01L27/0688 ,  H01L21/56 ,  H01L25/0652 ,  H01L23/31

Abstract: In an embodiment, a device includes: an interposer; a first integrated circuit device attached to the interposer; a second integrated circuit device attached to the interposer adjacent the first integrated circuit device; a heat dissipation die on the second integrated circuit device; and an encapsulant around the heat dissipation die, the second integrated circuit device, and the first integrated circuit device, a top surface of the encapsulant being coplanar with a top surface of the heat dissipation die and a top surface of the first integrated circuit device.

公开(公告)号：US20230369273A1

公开(公告)日：2023-11-16

申请号：US18359024

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L25/10 ,  H01L23/48 ,  H01L23/538

CPC classification number: H01L24/24 ,  H01L25/0652 ,  H01L23/3135 ,  H01L25/50 ,  H01L25/105 ,  H01L24/25 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/24101 ,  H01L24/16 ,  H01L2224/73259 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2225/1041 ,  H01L2225/06568 ,  H01L2224/16145 ,  H01L24/73 ,  H01L2224/25171 ,  H01L2224/08145 ,  H01L24/32 ,  H01L2224/32145 ,  H01L23/5385 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L24/08 ,  H01L2225/1058 ,  H01L2224/24175 ,  H01L2225/1035

Abstract: A package structure including a device die structure, an insulating encapsulant, and a first redistribution circuit is provided. The device die structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die is stacked over and electrically connected to the second semiconductor die. The insulating encapsulant laterally encapsulates the device die structure. The insulating encapsulant includes a first encapsulation portion and a second encapsulation portion connected to the first encapsulation portion. The first encapsulation portion is disposed on the second semiconductor die and laterally encapsulates the first semiconductor die. The second encapsulation portion laterally encapsulates the first insulating encapsulation and the second semiconductor die. The first redistribution circuit structure is disposed on the device die and a first surface of the insulating encapsulant, and the first redistribution circuit structure is electrically connected to the device die.

公开(公告)号：US20230326825A1

公开(公告)日：2023-10-12

申请号：US18332957

申请日：2023-06-12

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Chen-Hua Yu ,  Sung-Feng Yeh ,  Ming-Fa Chen

IPC: H01L23/367 ,  H01L23/373 ,  H01L25/065 ,  H01L25/18 ,  H01L21/683 ,  H01L23/538

CPC classification number: H01L23/3675 ,  H01L23/3736 ,  H01L25/0657 ,  H01L25/0652 ,  H01L23/3677 ,  H01L25/18 ,  H01L21/6835 ,  H01L23/538 ,  H01L2224/16238 ,  H01L24/73

Abstract: A package structure and method of manufacturing is provided, whereby heat dissipating features are provided for heat dissipation. Heat dissipating features include conductive vias formed in a die stack, thermal chips, and thermal metal bulk, which can be bonded to a wafer level device. Hybrid bonding including chip to chip, chip to wafer, and wafer to wafer provides thermal conductivity without having to traverse a bonding material, such as a eutectic material. Plasma dicing the package structure can provide a smooth sidewall profile for interfacing with a thermal interface material.

公开(公告)号：US11715723B2

公开(公告)日：2023-08-01

申请号：US17186984

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chao-Wen Shih ,  Sung-Feng Yeh

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/768 ,  H01L21/304 ,  H01L21/306

CPC classification number: H01L24/94 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/76898 ,  H01L24/06 ,  H01L24/33 ,  H01L2224/03845 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/2784 ,  H01L2224/27831 ,  H01L2224/27845 ,  H01L2224/29005 ,  H01L2224/29011 ,  H01L2224/29016 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/83203 ,  H01L2224/83896 ,  H01L2224/9211 ,  H01L2225/06544

Abstract: A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other.

公开(公告)号：US20230238306A1

公开(公告)日：2023-07-27

申请号：US18194792

申请日：2023-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L21/76898 ,  H01L24/03 ,  H01L2224/05647 ,  H01L2224/02381 ,  H01L2224/08146 ,  H01L2224/0557 ,  H01L2224/05569 ,  H01L2224/02372 ,  H01L2224/02311

Abstract: A semiconductor device includes a first passivation layer over a circuit and. conductive pad over the first passivation layer, wherein the conductive pad is electrically connected to the circuit. A second passivation layer is disposed over the conductive pad and the first passivation layer, and has a first opening and a second opening. The first opening exposes an upper surface of a layer that extends underneath the conductive pad, and the second opening exposes the conductive pad. A first insulating layer is disposed over the second passivation layer and filling the first and second openings. A through substrate via extends through the insulating layer, second passivation layer, passivation layer, and substrate. A side of the through substrate via and the second passivation layer have a gap that is filled with the first insulating layer. A conductive via extends through the first insulating layer and connecting to the conductive pad.

公开(公告)号：US11658150B2

公开(公告)日：2023-05-23

申请号：US17379394

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Feng Yeh ,  Chen-Hua Yu ,  Ming-Fa Chen

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/522 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L23/498

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/96 ,  H01L25/50 ,  H01L21/568 ,  H01L23/315 ,  H01L23/3135 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/291 ,  H01L2224/29076 ,  H01L2224/29186 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/73209 ,  H01L2224/73267 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/8203 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2224/92124 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10331 ,  H01L2924/10332 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/10338 ,  H01L2924/10339 ,  H01L2924/10342 ,  H01L2924/14 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1816 ,  H01L2924/18162 ,  H01L2224/97 ,  H01L2224/80 ,  H01L2224/19 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2224/80001 ,  H01L2224/29186 ,  H01L2924/00014 ,  H01L2224/291 ,  H01L2924/00014

Abstract: An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.

公开(公告)号：US11562982B2

公开(公告)日：2023-01-24

申请号：US16398159

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chia Hu ,  Ming-Fa Chen ,  Sung-Feng Yeh

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/683 ,  H01L25/00

Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes an integrated circuit structure, a first die stack and a dummy die. The first die stack includes a plurality of first die structures and is bonded to the integrated circuit structure at a first side of the first die stack. The dummy die includes a plurality of through substrate vias, is located aside the first die stack and is electrically connected to the integrated circuit structure at the first side of the first die stack. In some embodiments, the height of the through substrate vias of the dummy die is the same as the height of the first die stack.

公开(公告)号：US11557581B2

公开(公告)日：2023-01-17

申请号：US16882759

申请日：2020-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00

Abstract: A method is provided. A bottom tier package structure is bonded to a support substrate through a first bonding structure, wherein the bottom tier package structure includes a first semiconductor die encapsulated by a first insulating encapsulation, and the first bonding structure includes stacked first dielectric layers and at least one stacked first conductive features penetrating through the stacked first dielectric layers. The support substrate is placed on a grounded stage such that the first semiconductor die is grounded through the at least one first stacked conductive features, the support substrate and the grounded stage. A second semiconductor die is bonded to the bottom tier package structure through a second bonding structure, wherein the second bonding structure includes stacked second dielectric layers and at least one stacked second conductive features penetrating through the stacked second dielectric layers. The second semiconductor die is encapsulated with a second insulating encapsulation.