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    Calibrated-output analog-to-digital converter apparatus and methods
    21.
    发明授权
    Calibrated-output analog-to-digital converter apparatus and methods 有权
    校准输出模数转换器装置和方法

    公开(公告)号：US09438266B1

    公开(公告)日：2016-09-06

    申请号：US15040572

    申请日：2016-02-10

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Krishnaswamy Nagaraj ,  Manish Goel ,  Xiao Pu ,  Hun-Seok Kim

    IPC: H03M1/10 ,  H03M3/00

    CPC classification number: H03M3/464 ,  H03M3/38

    Abstract: A direct current (“DC”) calibration reference voltage is applied at an input terminal of an N-level sigma-delta analog-to-digital converter (“ADC”). The ADC includes a current-mode DAC (“I-DAC”) operating as a feedback element. A count of logical 1s associated with each of N output levels is taken at outputs of a modulator portion of the ADC during a first mismatch measurement interval. Mismatch measurement logic subsequently transposes pairs of current sources between level selection switch matrices. Doing so causes modulator output error components resulting from mismatches between I-DAC current sources (“delta”) to appear as differential level-specific output counts. The mismatch measurement logic compares the differential counts to determine values of delta. The ADC then factors decimated modulator output counts by values of delta in order to correct for the I-DAC current source mismatch(es).

    Abstract translation: 在N级Σ-Δ模数转换器（“ADC”）的输入端施加直流（“DC”）校准参考电压。 ADC包括作为反馈元件工作的电流模式DAC（“I-DAC”）。 在第一失配测量间隔期间，在ADC的调制器部分的输出处获取与N个输出电平中的每一个相关联的逻辑1的计数。 不匹配测量逻辑随后在电平选择开关矩阵之间转置电流源对。 这样做会导致由I-DAC电流源（“delta”）之间的不匹配导致的调制器输出误差分量作为差分电平特定输出计数。 不匹配测量逻辑比较差分计数以确定delta的值。 ADC然后通过delta值将衰减的调制器输出计数值除数，以校正I-DAC电流源不匹配。

    CRC-BASED FORWARD ERROR CORRECTION CIRCUITRY AND METHOD
    22.
    发明申请
    CRC-BASED FORWARD ERROR CORRECTION CIRCUITRY AND METHOD 有权
    基于CRC的前向纠错电路和方法

    公开(公告)号：US20150278008A1

    公开(公告)日：2015-10-01

    申请号：US14224960

    申请日：2014-03-25

    Applicant: Texas Instruments Incorporated

    Inventor： Jing-Fei Ren ,  Manish Goel ,  Yuming Zhu

    IPC: G06F11/10 ,  H03M13/09 ,  H04L1/00

    CPC classification number: H03M13/09 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0061 ,  H04L1/16

    Abstract: A communication system includes digital transmitter circuitry (26) including a CRC (cyclic redundancy check) generator circuit (28) generating a first CRC code based on a message and appending the CRC code to the message a first data packet, and circuitry (26-1,2,3) transforming the first data packet to provide a second data packet and transmitting it. Digital receiver circuitry (120) includes circuitry (12-1,2,3) receiving the second data packet, a CRC verification circuit (14-1) comparing a received digital CRC code portion of the second data packet to a calculated digital CRC code portion including any introduced error to detect the existence of any error in the second data packet. The message is presented for further processing if no error is detected, and a CRC-based FEC (forward error correction) circuit (14-2) receives the message and calculated digital CRC code from the verification circuit if an error is detected, corrects the detected error, and indicates the error is uncorrectable if the correction is unsuccessful.

    Abstract translation: 通信系统包括数字发射机电路（26），包括CRC（循环冗余校验）发生器电路（28），其基于消息生成第一CRC码，并将CRC码附加到消息第一数据包，以及电路（26- 1,2,3）转换第一数据分组以提供第二数据分组并发送它。 数字接收机电路（120）包括接收第二数据分组的电路（12-1,2,3），将第二数据分组的接收数字CRC码部分与计算出的数字CRC码进行比较的CRC校验电路（14-1） 部分包括任何引入的错误，以检测第二数据分组中是否存在任何错误。 如果没有检测到错误，则呈现用于进一步处理的消息，并且如果检测到错误，则基于CRC的FEC（前向纠错）电路（14-2）从验证电路接收消息和计算的数字CRC码，校正 检测到错误，并指示错误是不可校正的，如果更正不成功。

    Methods and apparatus to create a physically unclonable function
    23.
    发明授权
    Methods and apparatus to create a physically unclonable function 有权

    公开(公告)号：US12050495B2

    公开(公告)日：2024-07-30

    申请号：US17130076

    申请日：2020-12-22

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Clive Bittlestone ,  Joyce Kwong ,  Manish Goel

    IPC: G06F1/26 ,  G06F21/73 ,  H04L9/32

    CPC classification number: G06F1/26 ,  G06F21/73 ,  H04L9/3278

    Abstract: Methods and apparatus for creating a physically unclonable function for SRAM are disclosed. An example method includes decreasing a supply voltage of a memory array to a first voltage level, the first voltage level being below a normal operating voltage associated with the memory array, reading a first value of a bit cell after the supply voltage has been at the first voltage level, and determining a function based on the first value of the bit cell and a second value, the second value stored in the bit cell when the memory array is operating at a voltage level above the first voltage level, the function to represent an identification of a circuit including the memory array.

    Low energy accelerator processor architecture with short parallel instruction word
    24.
    发明授权
    Low energy accelerator processor architecture with short parallel instruction word 有权

    公开(公告)号：US10740280B2

    公开(公告)日：2020-08-11

    申请号：US15714212

    申请日：2017-09-25

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Johann Zipperer ,  Manish Goel

    IPC: G06F15/80 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38

    Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

    METHODS AND APPARATUS TO DETERMINE AND APPLY POLARITY-BASED ERROR CORRECTION CODE
    28.
    发明申请
    METHODS AND APPARATUS TO DETERMINE AND APPLY POLARITY-BASED ERROR CORRECTION CODE 审中-公开

    公开(公告)号：US20170353195A1

    公开(公告)日：2017-12-07

    申请号：US15480062

    申请日：2017-04-05

    Applicant: Texas Instruments Incorporated

    Inventor： Manish Goel ,  Yuming Zhu

    IPC: H03M13/13 ,  G11C29/52 ,  G06F11/10

    Abstract: Methods, apparatus, systems and articles of manufacture to determine and apply polarity-based error correction code are disclosed. In some examples, the methods and apparatus create an array by setting a first set of bit locations of a code word to have a first value and setting a second set of bit locations of the code word to have a second value different from the first value. In some examples, when the array satisfies a parity check, the methods and apparatus determine that bit locations having the first value from the array form a polarity-based error correction code.

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