公开(公告)号：US09882054B2

公开(公告)日：2018-01-30

申请号：US14981869

申请日：2015-12-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L21/306 ,  H01L29/66 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L29/785 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795

Abstract: A FinFET is provided. The FinFET includes a substrate. A plurality of fin structures are defined on the substrate. A gate structure crosses each fin structure. Two first recesses are disposed on two sides of the gate structure respectively, wherein each first recess further includes a plurality of second recesses disposed therein, and the position of each second recess corresponds to each fin structure. Two epitaxial layers are disposed at two sides of the gate structure respectively and in the first recesses, each epitaxial layer has a bottom surface including a second concave and convex profile, and each epitaxial layer directly contacts a bottom surface of each first recess and a bottom surface of each second recess.

公开(公告)号：US09871001B2

公开(公告)日：2018-01-16

申请号：US15145789

申请日：2016-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou

IPC: H01L21/66 ,  H01L23/544 ,  H01L21/027 ,  H01L21/308

CPC classification number: H01L23/544 ,  G03F7/70633 ,  H01L22/12 ,  H01L22/20 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: A method of manufacturing an integrated circuit includes the following steps. A substrate including a plurality of exposure fields is provided, and each of the exposure fields includes a target portion and a set of overlay marks. The substrate is exposed to form a first layer lithography pattern on the target portion for the respective exposure field by an exposure system. The overlay of the first layer lithography pattern and the target portion is measured by the set of overlay marks of each exposure field to obtain first overlay data for the respective exposure field by a measuring system. The first overlay data is fed to form a second layer lithography pattern.

公开(公告)号：US09772557B2

公开(公告)日：2017-09-26

申请号：US14714357

申请日：2015-05-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: G03F7/20

CPC classification number: G03F7/203 ,  G03F7/2002 ,  G03F7/70091 ,  G03F7/70125 ,  G03F7/7025

Abstract: An illumination system includes a light source used to generate a light and an opaque plate. The opaque plate is disposed between the light source and a photomask and includes an annular aperture and an aperture dipole. The annular aperture has an inner side and an outer side. The aperture dipole includes at least one first aperture and at least one second aperture. The first aperture and the second aperture connected to the annular aperture respectively and protruding out from the outer side of the annular aperture are disposed symmetrically with respect to a center of the annular aperture.

公开(公告)号：US09754841B2

公开(公告)日：2017-09-05

申请号：US15060572

申请日：2016-03-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  Yu-Ru Yang ,  En-Chiuan Liou

IPC: H01L21/8238 ,  H01L29/423 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

Abstract: The present invention provides a method of forming an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

公开(公告)号：US20170193153A1

公开(公告)日：2017-07-06

申请号：US14989765

申请日：2016-01-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Che-Yi Lin

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G03F1/36 ,  G03F7/70633

Abstract: A method of filtering overlay data by field is provided in the present invention. The method includes the following steps. A minimum number of measure points per field on a semiconductor substrate is decided. Field data filtering rules are set. Overlay raw data is inputted. A raw data filtration is performed to the overlay raw data by field according to the field data filtering rules. Modified exposure parameters are generated for each field according to overlay data of remaining measure points per field after the raw data filtration when the number of the remaining measure points per field is larger than or equal to the minimum number of the measure points per field. Accordingly, the modified exposure parameters will be more effective in reducing the overlay error because more outliers may be filtered out before generating the modified exposure parameters.

公开(公告)号：US09679816B2

公开(公告)日：2017-06-13

申请号：US15190209

申请日：2016-06-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/82 ,  H01L21/8234 ,  H01L21/308 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/3085 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer. The substrate has a fin field-effect transistor (finFET) region, a first region, a second region and a third region. The first region, the second region and the third region have a first surface, a second surface, and a third surface, respectively, where the first surface is relatively higher than the second surface and the second surface is relatively higher than the third surface. The fin shaped structures are disposed on a surface of the fin field-effect transistor region. The insulating layer covers the first surface, the second surface and the third surface.

公开(公告)号：US09653404B1

公开(公告)日：2017-05-16

申请号：US15245161

申请日：2016-08-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Jing Wang ,  En-Chiuan Liou ,  Mei-Chen Chen ,  Han-Lin Zeng ,  Chia-Hung Lin ,  Chun-Chi Yu

IPC: H01L23/544

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446

Abstract: The present invention provides an overlay target. The overlay target includes a plurality of first pattern blocks and a plurality of second pattern blocks. The first pattern blocks and the second patterns blocks are arranged in array by being separated by at least one first gaps stretching along a first direction and at least one second gaps stretching along a second direction. Each first pattern block is composed of a plurality of first stripe patterns stretching along a third direction, and each second pattern block is composed of a plurality of second stripe patterns stretching along a fourth direction. The first direction is orthogonal to the second direction, the third direction and the fourth direction are 45 degrees relative to the first direction.

公开(公告)号：US09608090B2

公开(公告)日：2017-03-28

申请号：US15170904

申请日：2016-06-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/417 ,  H01L21/285 ,  H01L29/165 ,  H01L29/267 ,  H01L29/161 ,  H01L29/24

CPC classification number: H01L29/6681 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823431 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7856 ,  H01L2029/7858

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate, and a sacrificial mandrel is formed on the substrate, in which the sacrificial mandrel includes a first side and a second side with the indentation. Next, a spacer is formed adjacent to the first side and the second side of the sacrificial mandrel, the sacrificial mandrel is removed, and the spacer is used to remove part of the substrate for forming a fin-shaped structure and a dummy fin-shaped structure.

公开(公告)号：US09583568B2

公开(公告)日：2017-02-28

申请号：US14612300

申请日：2015-02-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Ssu-I Fu ,  Chia-Lin Lu ,  Shih-Hung Tsai ,  Chih-Wei Yang ,  Chia-Ching Lin ,  Chia-Hsun Tseng ,  Rai-Min Huang

IPC: H01L29/66 ,  H01L21/84 ,  H01L27/06 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L27/12 ,  H01L21/76

CPC classification number: H01L29/0684 ,  H01L21/76 ,  H01L21/762 ,  H01L21/76232 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7846 ,  H01L29/7851

Abstract: The present invention provides a semiconductor structure, including a substrate, a shallow trench isolation (STI) disposed in the substrate, a plurality of first fin structures disposed in the substrate, where each first fin structure and the substrate have same material, and a plurality of second fin structures disposed in the STI, where each second fin structure and the STI have same material.

Abstract translation: 本发明提供一种半导体结构，包括基板，设置在基板中的浅沟槽隔离（STI），设置在基板中的多个第一翅片结构，其中每个第一翅片结构和基板具有相同的材料，以及多个 设置在STI中的第二鳍结构，其中每个第二鳍结构和STI具有相同的材料。

公开(公告)号：US09548216B1

公开(公告)日：2017-01-17

申请号：US14809270

申请日：2015-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Te Chen ,  Chia-Hsun Tseng ,  En-Chiuan Liou ,  Chiung-Lin Hsu ,  Meng-Lin Tsai ,  Jan-Fu Yang ,  Yu-Ting Hung ,  Shin-Feng Su

IPC: H01L21/76 ,  H01L21/321 ,  H01L21/225 ,  H01L21/3205 ,  H01L21/3105

CPC classification number: H01L21/2253 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821

Abstract: A method of adjusting channel widths of semiconductive devices includes providing a substrate divided into a first region and a second region, wherein the substrate comprises numerous fins. A first implantation process is performed on the fins within the first region. Then, a second implantation process is performed on the fins within the second region, wherein the first implantation process and the second implantation process are different from each other in at least one of the conditions comprising dopant species, dopant dosage or implantation energy. After that, part of the fins within the first region and the second region are removed simultaneously to form a plurality of first recesses within the first region and a plurality of second recesses within the second region. Finally, a first epitaxial layer and a second epitaxial layer are formed to fill up each first recess and each second recess, respectively.

Abstract translation: 调整半导体器件的沟道宽度的方法包括提供分成第一区域和第二区域的衬底，其中衬底包括多个鳍片。 在第一区域内的翅片上执行第一注入工艺。 然后，对第二区域内的翅片执行第二注入工艺，其中第一注入工艺和第二注入工艺在包括掺杂剂种类，掺杂剂剂量或注入能量的至少一个条件中彼此不同。 之后，同时去除第一区域和第二区域内的部分散热片，以在第一区域内形成多个第一凹槽，在第二区域内形成多个第二凹槽。 最后，形成第一外延层和第二外延层以分别填充每个第一凹槽和每个第二凹槽。