公开(公告)号：US10332750B2

公开(公告)日：2019-06-25

申请号：US15820443

申请日：2017-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Hsu Ting ,  Chung-Fu Chang ,  Shi-You Liu ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC: H01L21/3105 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L29/165 ,  H01L21/266 ,  H01L21/324 ,  H01L29/08

Abstract: A method for fabricating a semiconductor device. A gate is formed on a substrate. A spacer is formed on each sidewall of the gate. A hard mask layer is formed on the spacer. A recessed region is formed in the substrate and adjacent to the hard mask layer. An epitaxial layer is formed in the recessed region. The substrate is subjected to an ion implantation process to bombard particle defects on the hard mask layer with inert gas ions. An annealing process is performed to repair damages to the epitaxial layer caused by the ion implantation process. The hard mask layer is then removed.

公开(公告)号：US09899520B2

公开(公告)日：2018-02-20

申请号：US14978409

申请日：2015-12-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02636 ,  H01L21/0332 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

Abstract: A method for forming a semiconductor device includes steps as follows: Firstly, a semiconductor substrate having a circuit element with at least one spacer formed thereon is provided. Next, an acid treatment is performed on a surface of the spacer. A disposable layer is then formed on the circuit element and the spacer. Thereafter, an etching process is performed to form at least one recess in the semiconductor substrate adjacent to the circuit element. Subsequently, a selective epitaxial growth (SEG) process is performed to form an epitaxial layer in the recess.

公开(公告)号：US20170200824A1

公开(公告)日：2017-07-13

申请号：US15469569

申请日：2017-03-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Wei Yu ,  Hsu Ting ,  Chueh-Yang Liu ,  Yu-Ren Wang ,  Kuang-Hsiu Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/45 ,  H01L29/417

CPC classification number: H01L29/7845 ,  H01L21/02065 ,  H01L21/28123 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device includes: a substrate; a gate structure on the substrate; and an epitaxial layer in the substrate adjacent to the gate structure, in which the epitaxial layer includes a planar surface and protrusions adjacent to two sides of the planar surface. Preferably, a contact plug is embedded in part of the epitaxial layer, and a silicide is disposed under the contact plug, in which a bottom surface of the silicide includes an arc.

公开(公告)号：US20240304705A1

公开(公告)日：2024-09-12

申请号：US18665600

申请日：2024-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chih Chuang ,  Chia-Jong Liu ,  Kuang-Hsiu Chen ,  Chung-Ting Huang ,  Chi-Hsuan Tang ,  Kai-Hsiang Wang ,  Bing-Yang Jiang ,  Yu-Lin Cheng ,  Chun-Jen Chen ,  Yu-Shu Lin ,  Jhong-Yi Huang ,  Chao-Nan Chen ,  Guan-Ying Wu

IPC: H01L29/66 ,  H01L29/423

CPC classification number: H01L29/6656 ,  H01L29/42364

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.

公开(公告)号：US20240234505A1

公开(公告)日：2024-07-11

申请号：US18105887

申请日：2023-02-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsu Ting ,  Kuang-Hsiu Chen ,  Shou-Hung Wu ,  Shao-Wei Wang ,  Yu-Ren Wang

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes a fin structure disposed on a substrate, and an epitaxial semiconductor layer disposed over an upper part of the fin structure and having an undercut. The epitaxial semiconductor layer has a right-left symmetric, concave polygonal cross-section.

公开(公告)号：US20230369460A1

公开(公告)日：2023-11-16

申请号：US17835977

申请日：2022-06-09

Applicant: United Microelectronics Corp.

Inventor： Kuang-Hsiu Chen ,  Wei-Chung Sun ,  Chao Nan Chen ,  Chun-Wei Yu ,  Kuan Hsuan Ku ,  Shao-Wei Wang

IPC: H01L29/66

CPC classification number: H01L29/66636 ,  H01L29/66575 ,  H01L29/66446 ,  H01L29/66795

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure includes the following. A gate structure is formed on a substrate. A tilt implanting process is performed to implant group IV elements into the substrate to form a doped region, and the doped region is located on two sides of the gate structure and partially located under the gate structure. A part of the substrate on two sides of the gate structure is removed to form a first recess. A cleaning process is performed on the surface of the first recess. A wet etching process is performed on the first recess to form a second recess. A semiconductor layer is formed in the second recess.

公开(公告)号：US10312084B2

公开(公告)日：2019-06-04

申请号：US15439890

申请日：2017-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Yi-Liang Ye ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L21/265 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/033 ,  H01L29/78 ,  H01L29/08 ,  H01L29/267 ,  H01L29/51 ,  H01L29/66 ,  H01L29/24 ,  H01L21/3105 ,  H01L27/092 ,  H01L29/49

Abstract: A method for fabricating the semiconductor device is disclosed. A semiconductor substrate having a main surface is provided. A gate is formed on the main surface of the semiconductor substrate. An offset liner is formed on the sidewall of the gate. An ion implantation process is performed to form lightly doped drain (LDD) region in the semiconductor substrate. A spacer is formed on a sidewall of the gate. A cavity is recessed into the main surface of the semiconductor substrate. The cavity is adjacent to the spacer. An epitaxial layer is grown in the cavity. The spacer is then subjected to a surface treatment to form a dense oxide film on the spacer. A mask layer is deposited on the dense oxide film. The dense oxide film has a thickness that is smaller or equal to 12 angstroms.

公开(公告)号：US20180323058A1

公开(公告)日：2018-11-08

申请号：US15590004

申请日：2017-05-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC: H01L21/02 ,  C09G1/02 ,  C08K5/42 ,  C08K5/14

CPC classification number: H01L21/02074 ,  H01L21/02065 ,  H01L21/32115 ,  H01L29/00

Abstract: A method for post chemical mechanical polishing clean is provided in the present invention, which include the steps of providing a substrate, performing a chemical mechanical polishing process, and performing a plurality of cleaning processes sequentially substrate using solutions of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) with different ratios and at different temperatures.

公开(公告)号：US09960084B1

公开(公告)日：2018-05-01

申请号：US15339949

申请日：2016-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Chueh-Yang Liu ,  Wen-Jiun Shen ,  Yu-Ren Wang

IPC: H01L21/8238 ,  H01L29/161 ,  H01L29/49 ,  H01L29/66 ,  H01L21/311 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/6653 ,  H01L29/7848 ,  H01L29/785

Abstract: The present invention provides a method for forming a semiconductor device, comprising the following steps: firstly, a substrate is provided, having a NMOS region and a PMOS region defined thereon, next, a gate structure is formed on the substrate within the NMOS region, and a disposal spacer is formed on two sides of the gate structure, afterwards, a mask layer is formed on the PMOS region to expose the NMOS region, next, a recess is formed on two sides of the gate structure spaced from the gate structure by the disposal spacer within the NMOS region, the disposal spacer is then removed after the recess is formed, and an epitaxial layer is formed into the recess.

公开(公告)号：US20170309485A1

公开(公告)日：2017-10-26

申请号：US15137010

申请日：2016-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Chueh-Yang Liu ,  Yu-Ren Wang ,  Chun-Wei Yu ,  Kuang-Hsiu Chen ,  Yi-Liang Ye ,  Hsu Ting ,  Neng-Hui Yang

IPC: H01L21/268 ,  H01L21/687 ,  H01L21/67 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L21/2686 ,  H01L21/02057 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/67051 ,  H01L21/6708 ,  H01L21/67115 ,  H01L21/68785 ,  H01L29/0847 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7834

Abstract: An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a plurality of first light sources configured to emit irradiation in FIR range and a plurality of second light sources configured to emit irradiation in UV range.