公开(公告)号：US20160043123A1

公开(公告)日：2016-02-11

申请号：US14819138

申请日：2015-08-05

Applicant: XINTEC INC.

Inventor： Wei-Ming CHIEN ,  Po-Han LEE ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L27/146

CPC classification number: H01L27/14623 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687 ,  H01L2224/11

Abstract: A semiconductor structure includes a chip, a light transmissive plate, a spacer, and a light-shielding layer. The chip has an image sensor, a first surface and a second surface opposite to the first surface. The image sensor is located on the first surface. The light transmissive plate is disposed on the first surface and covers the image sensor. The spacer is between the light transmissive plate and the first surface, and surrounds the image sensor. The light-shielding layer is located on the first surface between the spacer and the image sensor.

Abstract translation: 半导体结构包括芯片，透光板，间隔物和遮光层。 芯片具有图像传感器，与第一表面相对的第一表面和第二表面。 图像传感器位于第一个表面。 透光板设置在第一表面上并覆盖图像传感器。 间隔物在透光板和第一表面之间，并且围绕图像传感器。 遮光层位于间隔件和图像传感器之间的第一表面上。

公开(公告)号：US20150206916A1

公开(公告)日：2015-07-23

申请号：US14595870

申请日：2015-01-13

Applicant: XINTEC INC.

Inventor： Po-Han LEE ,  Shu-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO ,  Chien-Hung LIU

IPC: H01L27/146 ,  H01L31/0203

CPC classification number: H01L27/14632 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/1469 ,  H01L2224/11

Abstract: A manufacturing method of a semiconductor device includes the following steps. A temporary bonding layer is used to adhere a carrier to a first surface of a wafer. A redistribution layer, an insulating layer, and a conductive structure are formed on a second surface of the wafer opposite to the first surface, such that a semiconductor element is formed. The semiconductor element is diced from the insulating layer to the carrier, such that the semiconductor element forms at least one sub-semiconductor element. UV light is used to irradiate the sub-semiconductor element, such that adhesion of the temporary bonding layer is eliminated. The carrier of the sub-semiconductor element is removed.

Abstract translation: 半导体器件的制造方法包括以下步骤。 临时粘合层用于将载体粘附到晶片的第一表面。 在与第一表面相对的晶片的第二表面上形成再分布层，绝缘层和导电结构，从而形成半导体元件。 半导体元件从绝缘层切割到载体，使得半导体元件形成至少一个子半导体元件。 UV光用于照射次半导体元件，从而消除了临时粘合层的粘附。 子半导体元件的载体被去除。

公开(公告)号：US20150132949A1

公开(公告)日：2015-05-14

申请号：US14592818

申请日：2015-01-08

Applicant: XINTEC INC.

Inventor： Chia-Sheng LIN ,  Po-Han LEE

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/481 ,  H01L21/76897 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/94 ,  H01L27/14618 ,  H01L27/14636 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/20 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/00

Abstract: A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion.

Abstract translation: 提供了芯片封装及其制造方法。 芯片封装包括具有第一表面和相对的第二表面的半导体衬底。 间隔件设置在半导体衬底的第二表面下方，并且覆盖板设置在间隔件下方。 形成与半导体衬底的侧壁相邻的凹部，从半导体衬底的第一表面延伸到至少间隔件。 然后，保护层设置在半导体衬底的第一表面和凹部中。

公开(公告)号：US20130153933A1

公开(公告)日：2013-06-20

申请号：US13720627

申请日：2012-12-19

Applicant: XINTEC INC.

Inventor： Po-Han LEE ,  Chien-Hung LIU

IPC: H01L31/12 ,  H01L31/18

CPC classification number: H01L31/12 ,  H01L31/1876

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a sensor region formed in the semiconductor substrate; a light emitting device disposed on the second surface of the semiconductor substrate; at least one first conducting bump disposed on the first surface of the semiconductor substrate and electrically connected to the sensor region; at least one second conducting bump disposed on the first surface of the semiconductor substrate and electrically connected to the light emitting device; and an insulating layer located on the semiconductor substrate to electrically insulate the semiconductor substrate from the at least one first conducting bump and the at least one second conducting bump.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 形成在所述半导体衬底中的传感器区域; 设置在所述半导体衬底的第二表面上的发光器件; 至少一个第一导电凸块，设置在所述半导体衬底的所述第一表面上并电连接到所述传感器区域; 设置在所述半导体衬底的所述第一表面上并电连接到所述发光器件的至少一个第二导电凸块; 以及绝缘层，其位于所述半导体衬底上以将所述半导体衬底与所述至少一个第一导电凸块和所述至少一个第二导电凸块电绝缘。

公开(公告)号：US20210159350A1

公开(公告)日：2021-05-27

申请号：US17075544

申请日：2020-10-20

Applicant: XINTEC INC.

Inventor： Po-Han LEE ,  Chia-Ming CHENG ,  Wei-Ming CHIEN

IPC: H01L31/0352 ,  H01L31/0216 ,  H01L31/02 ,  H01L31/18

Abstract: A chip package includes a chip and a conductive structure. A first surface of the chip has a photodiode. A second surface of the chip facing away from the first surface has a recess aligned with the photodiode. The conductive structure is located on the first surface of the chip.

公开(公告)号：US20210066379A1

公开(公告)日：2021-03-04

申请号：US16950810

申请日：2020-11-17

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Po-Han LEE

IPC: H01L27/146 ,  H01L23/00

Abstract: A manufacturing method of a chip package includes forming a temporary bonding layer on a carrier; forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer; bonding the carrier to the wafer, in which the encapsulation layer covers a sensor and a conductive pad of the wafer; patterning a bottom surface of the wafer to form a through hole, in which the conductive pad is exposed through the through hole; forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole; forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole; forming a passivation layer on the isolation layer and the redistribution layer; and removing the temporary bonding layer and the carrier.

公开(公告)号：US20180102321A1

公开(公告)日：2018-04-12

申请号：US15724058

申请日：2017-10-03

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Po-Han LEE ,  Chia-Ming CHENG ,  Hsin-Yen LIN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L23/495 ,  H01L23/00

Abstract: A chip package including a substrate having an upper surface, a lower surface, and a sidewall surface that is at the edge of the substrate is provided. The substrate includes a sensor device therein and adjacent to the upper surface thereof. The chip package further includes light-shielding layer disposed over the sidewall surface of the substrate and extends along the edge of the substrate to surround the sensor device. The chip package further includes a cover plate disposed over the upper surface of the substrate and a spacer layer disposed between the substrate and the cover plate. A method of forming the chip package is also provided.

公开(公告)号：US20170148694A1

公开(公告)日：2017-05-25

申请号：US15358098

申请日：2016-11-21

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Hsiao-Lan YEH ,  Chia-Sheng LIN ,  Yi-Ming CHANG ,  Po-Han LEE ,  Hui-Hsien WU ,  Jyun-Liang WU

IPC: H01L23/053 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L21/561 ,  G06K9/0004 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L2224/16225

Abstract: A chip package includes a chip, a first adhesive layer, a second adhesive layer, and a protection cap. The chip has a sensing area, a first surface, a second surface that is opposite to the first surface, and a side surface adjacent to the first and second surfaces. The sensing area is located on the first surface. The first adhesive layer covers the first surface of the chip. The second adhesive layer is located on the first adhesive layer, such that the first adhesive layer is between the first surface and the second adhesive layer. The protection cap has a bottom board and a sidewall that surrounds the bottom board. The bottom board covers the second adhesive layer, and the sidewall covers the side surface of the chip.

公开(公告)号：US20170092607A1

公开(公告)日：2017-03-30

申请号：US15272297

申请日：2016-09-21

Applicant: XINTEC INC.

Inventor： Hsin KUAN ,  Tsang-Yu LIU ,  Po-Han LEE

IPC: H01L23/00 ,  H01L21/78

CPC classification number: H01L24/09 ,  H01L21/6835 ,  H01L21/78 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14683 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A chip package is provided. The chip package includes a first substrate including a sensing region or device region. The chip package also includes a second substrate. The first substrate is mounted on the second substrate and is electrically connected to the second substrate. The ratio of the thickness of the first substrate to the thickness of the second substrate is in a range from 2 to 8.

公开(公告)号：US20160355393A1

公开(公告)日：2016-12-08

申请号：US15171971

申请日：2016-06-02

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Wei-Luen SUEN ,  Po-Han LEE

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0081 ,  B81B7/0077 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3677 ,  H01L23/481 ,  H01L2224/11

Abstract: A chip package includes a chip having an upper surface and a lower surface. A sensing element is disposed on the upper surface of the chip, and a thermal dissipation layer is disposed below the lower surface of the chip. A plurality of thermal dissipation external connections are disposed below the thermal dissipation layer and in contact with the thermal dissipation layer.

Abstract translation: 芯片封装包括具有上表面和下表面的芯片。 感测元件设置在芯片的上表面上，并且散热层设置在芯片的下表面下方。 多个散热外部连接设置在散热层下方并与散热层接触。