公开(公告)号：US07999391B2

公开(公告)日：2011-08-16

申请号：US12278339

申请日：2007-02-06

申请人： Hiroto Ootake ,  Masayoshi Tagami ,  Munehiro Tada ,  Yoshihiro Hayashi

发明人： Hiroto Ootake ,  Masayoshi Tagami ,  Munehiro Tada ,  Yoshihiro Hayashi

IPC分类号： H01L29/40

CPC分类号： H01L23/53238 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a wiring of the Damascene structure for preventing the TDDB withstand voltage degradation and for keeping the planarity to prevent the degradation of a focus margin. A trench wiring (213) is formed in an interlayer insulating film, which is composed of a silicon carbide-nitride film (205), a SiOCH film (206) and a silicon oxide film (207) [(e)]. The silicon oxide film (207) is etched at a portion adjacent to the wiring of a polished surface by dry etching or wet etching [(f)]. A silicon carbide-nitride film (SiCN) (214) is formed as a Cu cap film [(g)]. An interlayer insulating film is further formed thereon to form a conductive plug, a trench wiring and so on.

摘要翻译： 提供了一种用于防止TDDB耐电压劣化并保持平面性以防止聚焦余量劣化的镶嵌结构的布线。 沟槽布线（213）形成在由碳化硅 - 氮化物膜（SiO 2），SiOCH膜（206）和氧化硅膜（207）[（e）]组成的层间绝缘膜中。 氧化硅膜（207）通过干蚀刻或湿蚀刻（f）]在与抛光表面的布线相邻的部分被蚀刻。 形成碳化硅 - 氮化物膜（SiCN）（214）作为Cu帽膜[（g）]。 还在其上形成层间绝缘膜以形成导电插塞，沟槽布线等。

公开(公告)号：USD635121S1

公开(公告)日：2011-03-29

申请号：US29368765

申请日：2010-08-30

申请人： Noriaki Takahashi ,  Yoshihiro Hayashi

设计人： Noriaki Takahashi ,  Yoshihiro Hayashi

公开(公告)号：US20100327409A1

公开(公告)日：2010-12-30

申请号：US12864091

申请日：2009-01-22

申请人： Ippei Kume ,  Naoya Inoue ,  Yoshihiro Hayashi

发明人： Ippei Kume ,  Naoya Inoue ,  Yoshihiro Hayashi

IPC分类号： H01L29/92 ,  H01L21/314

CPC分类号： H01L28/60 ,  H01L21/28506 ,  H01L21/31637 ,  H01L21/32053 ,  H01L21/32105 ,  H01L23/5223 ,  H01L23/5283 ,  H01L23/5286 ,  H01L27/0688 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

摘要： A capacitive element formed within a semiconductor device comprises an upper electrode, a capacitive insulating film containing an oxide and/or silicate of a transition metal element, and a lower electrode having a polycrystalline conductive film composed of a material having higher oxidation resistance than the transition metal element and an amorphous or microcrystalline conductive film formed below the polycrystalline conductive film.

摘要翻译： 形成在半导体器件内的电容元件包括上电极，含有过渡金属元素的氧化物和/或硅酸盐的电容绝缘膜，以及具有多晶导电膜的下电极，所述多晶导体膜由比所述转变 金属元素和形成在多晶导电膜下面的非晶或微晶导电膜。

公开(公告)号：US20100148171A1

公开(公告)日：2010-06-17

申请号：US12654205

申请日：2009-12-14

申请人： Yoshihiro Hayashi ,  Naoya Inoue ,  Kishou Kaneko

发明人： Yoshihiro Hayashi ,  Naoya Inoue ,  Kishou Kaneko

IPC分类号： H01L29/24 ,  H01L21/336

CPC分类号： H01L21/76807 ,  H01L21/28282 ,  H01L21/76877 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/242 ,  H01L29/41 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/792

摘要： A semiconductor device of the present invention has a first interconnect layer formed over the semiconductor substrate, and a semiconductor element; the first interconnect layer has an insulating layer, and a first interconnect filled in a surficial portion of the insulating layer; the semiconductor element has a semiconductor layer, a gate insulating film, and a gate electrode; the semiconductor layer is positioned over the first interconnect layer; the gate insulating film is positioned over or below semiconductor layer; and the gate electrode is positioned on the opposite side of the semiconductor layer while placing the gate insulating film in between.

摘要翻译： 本发明的半导体器件具有形成在半导体衬底上的第一互连层和半导体元件; 所述第一互连层具有绝缘层，以及填充在所述绝缘层的表面部分中的第一互连层; 半导体元件具有半导体层，栅极绝缘膜和栅电极; 半导体层位于第一互连层上方; 栅绝缘膜位于半导体层之上或之下; 并且栅极电极位于半导体层的相反侧，同时将栅极绝缘膜放置在其间。

公开(公告)号：US20100025852A1

公开(公告)日：2010-02-04

申请号：US12518688

申请日：2007-12-20

申请人： Makoto Ueki ,  Hironori Yamamoto ,  Yoshihiro Hayashi ,  Fuminori Ito ,  Yoshiyuki Fukumoto

发明人： Makoto Ueki ,  Hironori Yamamoto ,  Yoshihiro Hayashi ,  Fuminori Ito ,  Yoshiyuki Fukumoto

IPC分类号： H01L23/48 ,  H01L21/312 ,  H01L21/768

CPC分类号： H01L21/31633 ,  C23C16/30 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/3122 ,  H01L21/31695 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76883 ,  H01L21/76886 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： To suppress deterioration in reliability of wiring and to reduce effective dielectric constant of wiring. In a semiconductor device, copper-containing wirings are covered by barrier insulating films, and the barrier insulating films contain a component of an organic silica containing unsaturated hydrocarbon and amorphous carbon. The copper-containing wirings are covered by the barrier insulating films that contain a component that is in an organic silica structure containing unsaturated hydrocarbon and amorphous carbon. Accordingly, inter-wiring capacitance is reduced without deteriorating reliability of the copper-containing wiring, thereby realizing a high-speed LSI with low power consumption.

摘要翻译： 抑制布线可靠性的劣化，降低布线的有效介电常数。 在半导体器件中，含铜布线被阻挡绝缘膜覆盖，隔离绝缘膜含有含有不饱和烃和无定形碳的有机二氧化硅的成分。 含铜配线被含有含有不饱和烃和无定形碳的有机二氧化硅结构的成分的阻隔绝缘膜覆盖。 因此，在不劣化含铜布线的可靠性的情况下降低布线间电容，从而实现低功耗的高速LSI。

公开(公告)号：US07622808B2

公开(公告)日：2009-11-24

申请号：US11317399

申请日：2005-12-23

申请人： Hiroto Ohtake ,  Masayoshi Tagami ,  Munehiro Tada ,  Yoshihiro Hayashi

发明人： Hiroto Ohtake ,  Masayoshi Tagami ,  Munehiro Tada ,  Yoshihiro Hayashi

IPC分类号： H01L23/48

CPC分类号： H01L21/76813 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3143 ,  H01L21/31633 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A semiconductor device includes a first interconnection layer and a interlayer insulating layer. The first interconnection layer is formed on a upper side of a substrate, and includes a first interconnection. The interlayer insulating layer is formed on the first interconnection layer, and includes a via connected with the first interconnection at one end of the via and a second interconnection connected with the via at another end of the via. The interlayer insulating layer has a relative dielectric constant lower than that of a silicon oxide film. An upper portion of the interlayer insulating layer includes a silicon-oxide film, a silicon nitride film and a silicon oxide film in order from a lower portion.

摘要翻译： 半导体器件包括第一互连层和层间绝缘层。 第一互连层形成在基板的上侧，并且包括第一互连。 层间绝缘层形成在第一互连层上，并且包括在通孔的一端与第一互连连接的通孔和在通孔的另一端与通孔相连的第二互连。 层间绝缘层的相对介电常数比氧化硅膜低。 层间绝缘层的上部从下部开始依次包括氧化硅膜，氮化硅膜和氧化硅膜。

公开(公告)号：US20080136043A1

公开(公告)日：2008-06-12

申请号：US11908099

申请日：2006-03-09

申请人： Hiroto Ohtake ,  Yoshihiro Hayashi

发明人： Hiroto Ohtake ,  Yoshihiro Hayashi

IPC分类号： H01L21/4763 ,  H01L23/48 ,  G06F17/50 ,  G03F1/00

CPC分类号： H01L21/76835 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multilayer interconnection structure according to this invention is applied to a case where a plurality of interconnections are formed at a fine pitch and a via is connected to at least one of the interconnections. In the multilayer interconnection structure, a region facing the via is locally narrowed in at least the interconnection, facing the via, of the interconnections adjacent to the interconnection connected to the via.

摘要翻译： 根据本发明的多层互连结构应用于以细间距形成多个互连并且通孔连接到至少一个互连的情况。 在多层互连结构中，面向通孔的区域至少在与连接到通孔的互连件相邻的互连件的互连（面对通孔）的局部变窄。

公开(公告)号：US07270849B2

公开(公告)日：2007-09-18

申请号：US10521238

申请日：2003-07-15

申请人： Yoshihiro Hayashi

发明人： Yoshihiro Hayashi

IPC分类号： C23C14/06

CPC分类号： H01L21/76801 ,  C08G77/06 ,  C09D4/00 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/3124 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835 ,  Y10T428/31663 ,  C08G77/04

摘要： An insulated organic copolymer is provided, having the excellent mechanical strength and deposition property at an interface contacting the lower base or the upper layer of the inorganic insulation film, and the effective dielectric constant is low as the whole film, which is suitable as the interlayer insulation film that separates the multi-layer copper wirings of the semiconductor device. The organosiloxane copolymer film is obtained by the polymerization of the cyclosiloxane and the straight-chain siloxane as the raw materials by the plasma excitation of both. At the interfaces contacting the inorganic insulation films, the interface layers having a film quality that is intricate and excellent in deposition property are prepared whereby the main component of the film composition is the straight-chain siloxane. The inner section of the copolymer film mixes the cyclosiloxane component having pores surrounded by the cyclosiloxane backbone and the straight-chain siloxane components, has the network structure layer relatively suppressing the density, and has the composition changing in the thickness direction whereby the multi-layer wirings embedding the copper thin film is formed.

摘要翻译： 提供了一种绝缘的有机共聚物，其在与无机绝缘膜的下基底或上层接触的界面处具有优异的机械强度和沉积性能，并且作为整个膜的有效介电常数低，适合作为中间层 隔离半导体器件的多层铜布线的绝缘膜。 有机硅氧烷共聚物膜是通过以二等离子体激发作为原料的环硅氧烷和直链硅氧烷的聚合而得到的。 在与无机绝缘膜接触的界面处制备具有复杂且成膜性优异的膜质量的界面层，由此膜组合物的主要成分为直链硅氧烷。 共聚物膜的内部将具有由环硅氧烷主链包围的孔的环硅氧烷成分和直链状硅氧烷成分混合，使网络结构层相对地抑制密度，并且在厚度方向上具有组成变化，由此多层 形成嵌入铜薄膜的布线。

公开(公告)号：US07184320B2

公开(公告)日：2007-02-27

申请号：US11167187

申请日：2005-06-28

申请人： Hajime Yamagami ,  Kouichi Terada ,  Yoshihiro Hayashi ,  Takashi Tsunehiro ,  Kunihiro Katayama ,  Kenichi Kaki ,  Takeshi Furuno

发明人： Hajime Yamagami ,  Kouichi Terada ,  Yoshihiro Hayashi ,  Takashi Tsunehiro ,  Kunihiro Katayama ,  Kenichi Kaki ,  Takeshi Furuno

IPC分类号： G11C11/34

CPC分类号： G11C29/765 ,  G06F3/0601 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2003/0694 ,  G06F2212/2022 ,  G11C16/102 ,  G11C16/349

摘要： A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased.

摘要翻译： 采用其中以块为单位重写数据的闪存的半导体盘作为存储介质，该半导体盘包括存储有文件数据的数据存储器，代替数据存储器中的错误块的替换存储器， 存储有数据存储器的错误信息的错误存储器，以及从数据存储器，替代存储器和错误存储器读取数据并将数据写入数据存储器，替代存储器和错误存储器的数据的存储器控​​制器。 由于可以补救闪速存储器的写入错误，所以可以提高半导体盘的使用寿命。

公开(公告)号：US20070013069A1

公开(公告)日：2007-01-18

申请号：US10558367

申请日：2004-05-28

申请人： Munehiro Tada ,  Yoshihiro Hayashi ,  Yoshimichi Harada ,  Fuminori Ito ,  Hiroto Ohtake ,  Tatsuya Usami

发明人： Munehiro Tada ,  Yoshihiro Hayashi ,  Yoshimichi Harada ,  Fuminori Ito ,  Hiroto Ohtake ,  Tatsuya Usami

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L23/53295 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multilayer wiring structure for connecting a semiconductor device is disclosed which is obtained by forming metal wirings on a substrate in which the semiconductor device is formed. The wiring structure free from such conventional problems that insulation between wirings next to each other is damaged or insulation resistance between wirings next to each other is deteriorated by generation of leakage current when fine metal wirings are formed in a porous insulating film. A method for producing such a wiring structure is also disclosed. In the metal wiring structure on the substrate in which the semiconductor device is formed, a insulating barrier layer (413) containing an organic matter is formed between an interlayer insulating film and a metal wiring. This insulating barrier layer reduces leakage current between wirings next to each other, thereby improving insulation reliability.

摘要翻译： 公开了一种用于连接半导体器件的多层布线结构，其通过在其中形成半导体器件的基板上形成金属布线而获得。 布线结构没有这样的常规问题，即在多孔绝缘膜中形成细金属布线时，通过产生漏电流而使彼此相邻的布线之间的绝缘损坏或彼此相邻的布线之间的绝缘电阻恶化。 还公开了一种用于制造这种布线结构的方法。 在形成了半导体器件的基板上的金属布线结构中，在层间绝缘膜和金属布线之间形成含有有机物质的绝缘阻挡层（413）。 该绝缘阻挡层减少彼此相邻的布线之间的漏电流，从而提高绝缘可靠性。