公开(公告)号：US20130100555A1

公开(公告)日：2013-04-25

申请号：US13279978

申请日：2011-10-24

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Shigeki TANEMURA ,  Kazuki SATO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Shigeki TANEMURA ,  Kazuki SATO ,  Atsushi IIJIMA

IPC分类号： G11B5/31 ,  G11B5/127 ,  G11B5/48

CPC分类号： G11B5/1278 ,  G11B5/3116 ,  G11B5/315 ,  G11B5/3163 ,  Y10T29/49023 ,  Y10T29/49032 ,  Y10T29/49043 ,  Y10T29/49044 ,  Y10T29/49046 ,  Y10T29/49048 ,  Y10T29/49052

摘要： A thin-film magnetic head is constructed such that a main magnetic pole layer, a lower shield layer, an upper shield layer and a thin-film coil are laminated on a substrate. A method of manufacturing the thin-film magnetic head has a lower shield layer forming step. This step comprises a step of forming a first lower shield part in a lower shield planned area, including a planned line along the medium-opposing surface, a step of forming a partial lower seed layer having a partial arrangement structure in which the partial lower seed layer is arranged on a lower formation zone except a lower exception zone including the planned line, a step of forming a second lower shield part on the partial lower seed layer.

摘要翻译： 薄膜磁头被构造成使得主磁极层，下屏蔽层，上屏蔽层和薄膜线圈层叠在基板上。 制造薄膜磁头的方法具有较低的屏蔽层形成步骤。 该步骤包括在下屏蔽计划区域中形成第一下屏蔽部分的步骤，包括沿着中间相对表面的计划线，形成具有部分布置结构的部分下部种子层的步骤，其中部分下部种子 层布置在下形成区域，除了包括预定线的下异常区域，在部分下种子层上形成第二下屏蔽部分的步骤。

公开(公告)号：US20130020723A1

公开(公告)日：2013-01-24

申请号：US13184971

申请日：2011-07-18

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

IPC分类号： H01L23/52

CPC分类号： H01L23/5389 ,  H01L21/6835 ,  H01L22/22 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05008 ,  H01L2224/05013 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/1146 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/16148 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/2512 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2224/25177 ,  H01L2224/2746 ,  H01L2224/29024 ,  H01L2224/29144 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/75101 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/8313 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83986 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/07802 ,  H01L2924/0105 ,  H01L2224/82 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/0231 ,  H01L2224/27 ,  H01L21/78 ,  H01L2224/81 ,  H01L2924/00

摘要： A composite layered chip package includes a plurality of subpackages stacked on each other. Each subpackage includes a main body and wiring. The main body includes a main part including a plurality of layer portions, and further includes first terminals and second terminals that are disposed on top and bottom surfaces of the main part, respectively. The wiring is electrically connected to the first and second terminals. The number of the plurality of layer portions included in the main part is the same for all the plurality of subpackages, and the plurality of layer portions in every subpackage include at least one first-type layer portion. In each of at least two of the subpackages, the plurality of layer portions further include at least one second-type layer portion. The first-type layer portion includes a semiconductor chip connected to the wiring, whereas the second-type layer portion includes a semiconductor chip not connected to the wiring.

摘要翻译： 复合分层芯片封装包括彼此堆叠的多个子封装。 每个子包包括主体和接线。 主体包括包括多个层部分的主要部分，并且还包括分别设置在主要部分的顶表面和底表面上的第一端子和第二端子。 布线电连接到第一和第二端子。 包括在主要部分中的多个层部分的数量对于所有多个子包是相同的，并且每个子包中的多个层部分包括至少一个第一类型层部分。 在至少两个子包中的每一个中，多个层部分还包括至少一个第二类型层部分。 第一型层部分包括连接到布线的半导体芯片，而第二型层部分包括未连接到布线的半导体芯片。

公开(公告)号：US20120256321A1

公开(公告)日：2012-10-11

申请号：US13084053

申请日：2011-04-11

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hiroshi IKEJIMA ,  Atsushi IIJIMA

IPC分类号： H01L23/48 ,  H01L21/50 ,  H01L21/78

CPC分类号： H01L21/561 ,  H01L23/3121 ,  H01L24/24 ,  H01L24/82 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/83005

摘要： A layered chip package includes a main body and wiring. The main body includes a main part including a plurality of stacked layer portions, and a plurality of terminals disposed on the top and bottom surfaces of the main part. The wiring includes a plurality of lines electrically connected to the plurality of terminals. The plurality of lines include a plurality of common lines and a plurality of layer-dependent lines. Each of the plurality of layer portions includes: a plurality of common electrodes electrically connected to the plurality of common lines; a plurality of non-contact electrodes that are electrically connected to the layer-dependent lines and are not in contact with the semiconductor chip in the layer portion; and a selective connection electrode selectively electrically connected to only the layer-dependent line that the layer portion uses among the plurality of layer-dependent lines. The layer-dependent lines are greater than the common lines in maximum width.

摘要翻译： 分层芯片封装包括主体和布线。 主体包括主要部分，其包括多个堆叠层部分，以及设置在主要部分的顶表面和底表面上的多个端子。 布线包括电连接到多个端子的多条线。 多条线包括多条公共线和多个依赖于层的线。 多个层部分中的每一个包括：电连接到多个公共线的多个公共电极; 多个非接触电极，其电连接到与层相关的线，并且不与层部分中的半导体芯片接触; 以及选择性连接电极，其仅选择性地电连接到所述层部分在多个层相关线中使用的与层相关的线。 层相关线大于最大宽度的公共线。

公开(公告)号：US20120025355A1

公开(公告)日：2012-02-02

申请号：US12848595

申请日：2010-08-02

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

IPC分类号： H01L23/544 ,  H01L21/00 ,  H01L23/552

CPC分类号： H01L23/552 ,  H01L21/6835 ,  H01L23/481 ,  H01L24/05 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/83005 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01029 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/3025 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00

摘要： In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein. Further, an uppermost substrate and a lowermost substrate have electromagnetic shielding layer formed in regions other than the scribe-groove parts using a ferromagnetic body. Further, in the laminated semiconductor substrate, a through hole which penetrates the plurality of semiconductor substrates laminated in a laminated direction is formed in the scribe-groove part, and the laminated semiconductor substrate has a through electrode penetrating the plurality of semiconductor substrates through the through hole.

摘要翻译： 在层叠半导体衬底中层叠多个半导体衬底。 每个半导体衬底具有沿着划线形成的多个划线槽部分。 此外，每个半导体衬底具有彼此绝缘的多个器件区域，并且其中形成有半导体器件。 此外，最上面的基板和最下面的基板在使用铁磁体的划线槽部以外的区域中形成有电磁屏蔽层。 此外，在层叠半导体基板中，在划线槽部形成有贯穿层叠方向的多个半导体基板的贯通孔，并且层叠半导体基板具有穿过多个半导体基板的通孔， 孔。

公开(公告)号：US20110189822A1

公开(公告)日：2011-08-04

申请号：US12700297

申请日：2010-02-04

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Atsushi IIJIMA

IPC分类号： H01L21/78

CPC分类号： H01L21/78 ,  H01L2224/16

摘要： A layered chip package includes a main body and wiring. The main body includes a plurality of layer portions stacked. The wiring is disposed on at least one side surface of the main body. In the method of manufacturing the layered chip package, first, a plurality of substructures each of which includes an array of a plurality of preliminary layer portions are used to fabricate a layered substructure that includes a plurality of pre-separation main bodies arranged in rows. Next, the layered substructure is cut into a plurality of blocks each of which includes a row of a plurality of pre-separation main bodies, and the wiring is formed on the plurality of pre-separation main bodies included in each block simultaneously. The plurality of pre-separation main bodies are then separated from each other. Each of the plurality of blocks includes a row of three, four, or five pre-separation main bodies.

摘要翻译： 分层芯片封装包括主体和布线。 主体包括堆叠的多个层部分。 布线布置在主体的至少一个侧表面上。 在制造层状芯片封装的方法中，首先，使用多个子结构，每个子结构包括多个预备层部分的阵列，以制造包括排成行的多个预分离主体的分层子结构。 接下来，将分层子结构切割成多个块，每个块包括一行多个预分离主体，并且布线同时形成在包括在每个块中的多个预分离主体上。 然后将多个预分离主体彼此分离。 多个块中的每个块包括一行三个，四个或五个预分离主体。

公开(公告)号：US20190228795A1

公开(公告)日：2019-07-25

申请号：US15880458

申请日：2018-01-25

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Kazuki SATO ,  Hironori ARAKI ,  Yukinori IKEGAWA ,  Yoji NOMURA

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Kazuki SATO ,  Hironori ARAKI ,  Yukinori IKEGAWA ,  Yoji NOMURA

IPC分类号： G11B5/39

CPC分类号： G11B5/3116 ,  G11B5/11 ,  G11B5/112 ,  G11B5/1278 ,  G11B5/315 ,  G11B5/3163 ,  G11B5/6082 ,  Y10T29/49046 ,  Y10T29/49052

摘要： A first side shield has a first sidewall and a second sidewall, and a second side shield has a third sidewall and a fourth sidewall. The first to fourth sidewalls have first to fourth edges, respectively, that are farthest from a top surface of a substrate. The distance between a rear end of the first edge and a rear end of the third edge in a track width direction is greater than the distance between a front end of the first edge and a front end of the third edge in the track width direction. The distance between the second edge and the fourth edge in the track width direction increases with increasing distance from the medium facing surface.

公开(公告)号：US20160343391A1

公开(公告)日：2016-11-24

申请号：US14720319

申请日：2015-05-22

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Shigeki TANEMURA ,  Kazuki SATO ,  Hideo MAMIYA ,  Kenichi TAKANO

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Shigeki TANEMURA ,  Kazuki SATO ,  Hideo MAMIYA ,  Kenichi TAKANO

IPC分类号： G11B5/31 ,  G11B5/48

CPC分类号： G11B5/315 ,  G11B5/314 ,  G11B5/3163 ,  G11B5/6088 ,  G11B11/10534 ,  G11B11/10536 ,  G11B11/10543 ,  G11B2005/0021

摘要： A thermally-assisted magnetic recording head includes a main pole, a plasmon generator, and first and second side shields. The main pole has a front end face located in the medium facing surface. The plasmon generator has a near-field light generating surface located in the medium facing surface. The front end face of the main pole includes a first end face portion, and a second end face portion greater in width than the first end face portion. The first and second side shields have first and second side shield end faces located on opposite sides of at least part of the near-field light generating surface and at least part of the first end face portion in the track width direction.

摘要翻译： 热辅助磁记录头包括主极，等离子体激元发生器以及第一和第二侧屏蔽。 主杆具有位于介质面对表面中的前端面。 等离子体发生器具有位于介质面对表面中的近场光产生表面。 主极的前端面包括第一端面部分和宽度大于第一端面部分的第二端面部分。 第一和第二侧面屏蔽具有位于近场光产生表面的至少一部分的相对侧上的第一和第二侧屏蔽端面以及轨道宽度方向上的第一端面部分的至少一部分。

公开(公告)号：US20160115612A1

公开(公告)日：2016-04-28

申请号：US14523415

申请日：2014-10-24

申请人： Yukinori IKEGAWA ,  Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hironori ARAKI ,  Seiichiro TOMITA ,  Hideo MAMIYA

发明人： Yukinori IKEGAWA ,  Yoshitaka SASAKI ,  Hiroyuki ITO ,  Hironori ARAKI ,  Seiichiro TOMITA ,  Hideo MAMIYA

IPC分类号： C25D7/00 ,  C23F4/00 ,  G11B5/39 ,  C25D5/02

CPC分类号： C25D7/001 ,  C25D5/022 ,  G11B5/3123

摘要： A thin-film magnetic head includes a coil, a magnetic path forming section, and an insulating film. The magnetic path forming section includes first and second magnetic material portions. The coil includes first and second coil elements located between the first and second magnetic material portions. The insulating film includes an underlying portion located under the first and second coil elements. In a method of manufacturing the thin-film magnetic head, the insulating film is formed to cover the first and second magnetic material portions, and then a seed layer is formed selectively on the underlying portion of the insulating film. The coil is formed by plating using the seed layer.

摘要翻译： 薄膜磁头包括线圈，磁路形成部分和绝缘膜。 磁路形成部分包括第一和第二磁性材料部分。 线圈包括位于第一和第二磁性材料部分之间的第一和第二线圈元件。 绝缘膜包括位于第一和第二线圈元件下方的下部。 在制造薄膜磁头的方法中，形成绝缘膜以覆盖第一和第二磁性材料部分，然后选择性地在绝缘膜的下面部分上形成晶种层。 线圈通过使用籽晶层进行电镀而形成。

公开(公告)号：US20150170679A1

公开(公告)日：2015-06-18

申请号：US14107701

申请日：2013-12-16

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Kazuki SATO ,  Shigeki TANEMURA ,  Yukinori IKEGAWA ,  Hironori ARAKI ,  Tatsuya SHIMIZU

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Kazuki SATO ,  Shigeki TANEMURA ,  Yukinori IKEGAWA ,  Hironori ARAKI ,  Tatsuya SHIMIZU

IPC分类号： G11B5/11 ,  G11B5/17

CPC分类号： G11B5/11 ,  G11B5/1278 ,  G11B5/17 ,  G11B5/3116 ,  G11B5/315 ,  G11B5/3163

摘要： A magnetic head includes a main pole, a write shield, and first and second nonmagnetic layers. The main pole has a top surface including an inclined surface portion. The write shield includes an inclined portion facing toward the top surface of the main pole. The first nonmagnetic layer is interposed between the inclined surface portion and the inclined portion. The second nonmagnetic layer is interposed between the first nonmagnetic layer and the inclined portion. The first nonmagnetic layer has a first front end located in a medium facing surface. The second nonmagnetic layer has a second front end that is located closest to but at a distance from the medium facing surface.

摘要翻译： 磁头包括主极，写屏蔽以及第一和第二非磁性层。 主极具有包括倾斜表面部分的顶表面。 写入屏蔽包括面向主极的顶表面的倾斜部分。 第一非磁性层插入在倾斜表面部分和倾斜部分之间。 第二非磁性层介于第一非磁性层和倾斜部分之间。 第一非磁性层具有位于介质相对表面中的第一前端。 第二非磁性层具有位于与介质相对表面最近但距离介质相对表面一定距离的第二前端。

公开(公告)号：US20150124575A1

公开(公告)日：2015-05-07

申请号：US14069883

申请日：2013-11-01

申请人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Shigeki TANEMURA ,  Hironori ARAKI ,  Hideo MAMIYA ,  Ryuji FUJII

发明人： Yoshitaka SASAKI ,  Hiroyuki ITO ,  Shigeki TANEMURA ,  Hironori ARAKI ,  Hideo MAMIYA ,  Ryuji FUJII

IPC分类号： G11B5/48 ,  G02B6/42 ,  G02B6/136 ,  G02B6/122

CPC分类号： G11B9/12 ,  G02B6/12004 ,  G02B6/1226 ,  G02B6/136 ,  G02B6/4291 ,  G11B5/3133 ,  G11B5/314 ,  G11B5/4866 ,  G11B5/6088 ,  G11B7/24059 ,  G11B2005/0021 ,  Y10T29/49

摘要： A plasmon generator includes a first portion and a second portion that are adjacent in a first direction orthogonal to the direction of travel of light propagating through a core. The second portion includes a front end face located in a medium facing surface of a magnetic head. The core has a concave portion recessed from the top surface of the core. At least part of the first portion is received in the concave portion. The concave portion has a surface including an evanescent light generating portion. The first portion includes a plasmon exciting portion opposed to the evanescent light generating portion. The evanescent light generating portion is inclined relative to a first surface.

摘要翻译： 等离子体发生器包括第一部分和第二部分，该第一部分和第二部分在与传播通过芯的光的行进方向正交的第一方向上相邻。 第二部分包括位于磁头的介质面向表面中的前端面。 芯具有从芯的顶表面凹陷的凹部。 第一部分的至少一部分被容纳在凹部中。 凹部具有包括渐逝光生成部的表面。 第一部分包括与瞬逝光产生部分相对的等离子体激元部分。 渐逝光产生部分相对于第一表面倾斜。