公开(公告)号：US20100187692A1

公开(公告)日：2010-07-29

申请号：US12756377

申请日：2010-04-08

申请人： Yu-Tang Pan ,  Cheng-Ting Wu ,  Shih-Wen Chou ,  Hui-Ping Liu

发明人： Yu-Tang Pan ,  Cheng-Ting Wu ,  Shih-Wen Chou ,  Hui-Ping Liu

IPC分类号： H01L23/498

CPC分类号： H01L21/6835 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49534 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer.

摘要翻译： 提供了包括基底，芯片，模塑料和多个外部端子的芯片封装。 该基底基本上由具有彼此相对的第一表面和第二表面的图案化电路层和设置在第二表面上的焊接掩模组成，其中该焊接掩模具有多个第一开口，通过该多个第一开口部分图案化电路层 被暴露。 芯片设置在第一表面上并且电连接到图案化电路层。 模塑料覆盖图案电路层并将芯片固定在图案化电路层上。 外部端子设置在第一开口中并电连接到图案化电路层。

公开(公告)号：US07605461B2

公开(公告)日：2009-10-20

申请号：US11755753

申请日：2007-05-31

申请人： Yu-Tang Pan ,  Shih-Wen Chou

发明人： Yu-Tang Pan ,  Shih-Wen Chou

IPC分类号： H01L23/02

CPC分类号： H01L23/49575 ,  H01L23/4334 ,  H01L23/495 ,  H01L24/31 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A chip package structure including a circuit pattern, a frame, a first adhesive layer, a plurality of leads, an insulating adhesive layer, a chip, a plurality of first bonding wires, a plurality of second bonding wires, and a molding compound is provided. The frame and leads are disposed around the circuit pattern. The first adhesive layer fastens the frame and the circuit pattern. The insulating adhesive layer is disposed between the leads and the frame. The chip has a plurality of bonding pads and is disposed on the first adhesive layer. The first bonding wires electrically connect the bonding pads individually to the circuit pattern. The second bonding wires electrically connect the leads individually to the circuit pattern. Thus, the bonding pads are electrically connected with the leads through the first bonding wires, the circuit pattern, and the second bonding wires. The molding compound covers foregoing components.

摘要翻译： 提供包括电路图案，框架，第一粘合剂层，多个引线，绝缘粘合剂层，芯片，多个第一接合线，多个第二接合线和模制化合物的芯片封装结构 。 框架和引线设置在电路图案周围。 第一粘合层紧固框架和电路图案。 绝缘粘合剂层设置在引线和框架之间。 芯片具有多个接合焊盘并设置在第一粘合剂层上。 第一接合线将接合焊盘分别电连接到电路图案。 第二接合线将引线单独地电连接到电路图案。 因此，接合焊盘通过第一接合线，电路图案和第二接合线与引线电连接。 模塑料覆盖上述组分。

公开(公告)号：US07592694B2

公开(公告)日：2009-09-22

申请号：US11746064

申请日：2007-05-09

申请人： Yu-Tang Pan ,  Men-Shew Liu ,  Shih-Wen Chou

发明人： Yu-Tang Pan ,  Men-Shew Liu ,  Shih-Wen Chou

IPC分类号： H01L23/495

CPC分类号： H01L23/49531 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0554 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A chip package including a metal layer, a film-like circuit layer, a chip, a lead matrix and an encapsulant is provided. The film-like circuit layer disposed on the metal layer includes an insulating film disposed on the metal layer and a circuit layer disposed on the insulating film. The circuit layer has a plurality of conductive traces. The chip disposed above the metal layer is electrically connected to the conductive traces. The lead matrix having a plurality of leads is disposed outside the chip. At least part of the leads are electrically connected to the conductive traces. The encapsulant at least encapsulates the chip, the film-like circuit layer, at least part of the leads, and at least part of the metal layer.

摘要翻译： 提供了包括金属层，膜状电路层，芯片，引线基体和密封剂的芯片封装。 设置在金属层上的膜状电路层包括设置在金属层上的绝缘膜和设置在绝缘膜上的电路层。 电路层具有多个导电迹线。 设置在金属层上方的芯片电连接到导电迹线。 具有多个引线的引线矩阵设置在芯片外部。 引线的至少一部分电连接到导电迹线。 密封剂至少封装芯片，膜状电路层，引线的至少一部分以及金属层的至少一部分。

公开(公告)号：US07510889B2

公开(公告)日：2009-03-31

申请号：US11762067

申请日：2007-06-13

申请人： Yu-Tang Pan ,  Shih-Wen Chou ,  Men-Shew Liu

发明人： Yu-Tang Pan ,  Shih-Wen Chou ,  Men-Shew Liu

IPC分类号： H01L21/00

CPC分类号： H01L33/486 ,  H01L24/97 ,  H01L33/62 ,  H01L33/64 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method for manufacturing a light emitting chip package includes bonding a patterned metal plate having at least a thermal enhanced plate and many contacts around the same to a substrate and bonding a film-like circuit layer to the patterned metal plate. Many conductive wires are formed to connect the film-like circuit layer and the contacts. Thereafter, at least a first molding is formed on the substrate to encapsulate the patterned metal plate, the conductive wires and a portion of the film-like circuit layer. At least one light emitting chip disposed on the film-like circuit layer exposed by the first molding has many bumps to which the light emitting chip and the film-like circuit layer are electrically connected. A cutting process is performed to form at least one light emitting chip package, and the substrate is removed. Therefore, heat dissipation efficiency of the light emitting chip package can be improved.

摘要翻译： 一种发光芯片封装的制造方法，其特征在于，将具有至少具有热增强板的图案化金属板和与其接触的多个触点结合，并将膜状电路层与图案化的金属板接合。 形成许多导线以连接膜状电路层和触点。 此后，在基板上形成至少第一模制件，以封装图案化的金属板，导电线和薄膜状电路层的一部分。 设置在通过第一模制件露出的膜状电路层上的至少一个发光芯片具有多个凸起，发光芯片和膜状电路层电连接到该凸起。 执行切割处理以形成至少一个发光芯片封装，并且去除衬底。 因此，可以提高发光芯片封装的散热效率。

公开(公告)号：US07436074B2

公开(公告)日：2008-10-14

申请号：US11302736

申请日：2005-12-13

申请人： Yu-Tang Pan ,  Cheng-Ting Wu ,  Shih-Wen Chou ,  Hui-Ping Liu

发明人： Yu-Tang Pan ,  Cheng-Ting Wu ,  Shih-Wen Chou ,  Hui-Ping Liu

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/6835 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49534 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package without a core, including a patterned circuit layer, a chip, a solder mask, a molding compound and multiple outer terminals, is provided. The patterned circuit layer has a first surface and a second surface opposite to each other. The chip disposed on the first surface is electrically connected to the patterned circuit layer. The solder mask disposed on the second surface has a plurality of first openings by which part of the patterned circuit layer is exposed. The molding compound with a plurality of through holes cover the pattern circuit layer and fix the chip onto the patterned circuit layer. Each outer terminal disposed in the through hole is electrically connected to the patterned circuit layer.

摘要翻译： 提供了不具有芯的芯片封装，包括图案化电路层，芯片，焊接掩模，模塑料和多个外部端子。 图案化电路层具有彼此相对的第一表面和第二表面。 布置在第一表面上的芯片电连接到图案化电路层。 设置在第二表面上的焊料掩模具有多个第一开口，图案化电路层的一部分露出。 具有多个通孔的成型复合物覆盖图形电路层，并将芯片固定在图案化电路层上。 布置在通孔中的每个外部端子电连接到图案化电路层。

公开(公告)号：US20080246131A1

公开(公告)日：2008-10-09

申请号：US11755753

申请日：2007-05-31

申请人： Yu-Tang Pan ,  Shih-Wen Chou

发明人： Yu-Tang Pan ,  Shih-Wen Chou

IPC分类号： H01L23/495

CPC分类号： H01L23/49575 ,  H01L23/4334 ,  H01L23/495 ,  H01L24/31 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A chip package structure including a circuit pattern, a frame, a first adhesive layer, a plurality of leads, an insulating adhesive layer, a chip, a plurality of first bonding wires, a plurality of second bonding wires, and a molding compound is provided. The frame and leads are disposed around the circuit pattern. The first adhesive layer fastens the frame and the circuit pattern. The insulating adhesive layer is disposed between the leads and the frame. The chip has a plurality of bonding pads and is disposed on the first adhesive layer. The first bonding wires electrically connect the bonding pads individually to the circuit pattern. The second bonding wires electrically connect the leads individually to the circuit pattern. Thus, the bonding pads are electrically connected with the leads through the first bonding wires, the circuit pattern, and the second bonding wires. The molding compound covers foregoing components.

摘要翻译： 提供包括电路图案，框架，第一粘合剂层，多个引线，绝缘粘合剂层，芯片，多个第一接合线，多个第二接合线和模制化合物的芯片封装结构 。 框架和引线设置在电路图案周围。 第一粘合层紧固框架和电路图案。 绝缘粘合剂层设置在引线和框架之间。 芯片具有多个接合焊盘并设置在第一粘合剂层上。 第一接合线将接合焊盘分别电连接到电路图案。 第二接合线将引线单独地电连接到电路图案。 因此，接合焊盘通过第一接合线，电路图案和第二接合线与引线电连接。 模塑料覆盖上述组分。

公开(公告)号：US20080017961A1

公开(公告)日：2008-01-24

申请号：US11530165

申请日：2006-09-08

申请人： Chun-Hung Lin ,  Shih-Wen Chou ,  Yu-Tang Pan

发明人： Chun-Hung Lin ,  Shih-Wen Chou ,  Yu-Tang Pan

IPC分类号： H01L21/00

CPC分类号： H01L23/49816 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A manufacturing method of a chip package structure is provided. A circuit substrate having a first surface, a second surface, and a through hole connecting the first surface and the second surface is provided. A chip having an active surface and bonding pads disposed on the active surface is provided. The chip is fixed on the circuit substrate, wherein the second surface is opposite to the active surface and the bonding pads are exposed to the through hole. Bonding wires connecting the bonding pads and the first surface are formed through the through hole. A film having an opening is formed on the first surface. The bonding wires, the bonding pads, the through hole, and part of the first surface are exposed by the opening. An encapsulant is formed to encapsulate part of the active surface, the bonding wires, and part of the first surface. The film is removed.

摘要翻译： 提供了一种芯片封装结构的制造方法。 提供具有第一表面，第二表面和连接第一表面和第二表面的通孔的电路基板。 提供具有有源表面的芯片和设置在有源表面上的接合焊盘。 芯片固定在电路基板上，其中第二表面与有源表面相对，并且焊盘暴露于通孔。 通过通孔形成连接接合焊盘和第一表面的接合线。 具有开口的膜形成在第一表面上。 接合线，接合焊盘，通孔和第一表面的一部分由开口露出。 形成密封剂以封装部分活性表面，接合线和第一表面的一部分。 电影被删除。

公开(公告)号：US20070228581A1

公开(公告)日：2007-10-04

申请号：US11761299

申请日：2007-06-11

申请人： Shih-Wen Chou ,  Chun-Hung Lin ,  Wu-Chang Tu ,  Yu-Tang Pan

发明人： Shih-Wen Chou ,  Chun-Hung Lin ,  Wu-Chang Tu ,  Yu-Tang Pan

IPC分类号： H01L23/52

CPC分类号： H01L23/13 ,  H01L23/3114 ,  H01L23/49816 ,  H01L24/10 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85186 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A universal chip package structure including a carrier, a chip, a plurality of bonding wires, and a molding compound is provided. The carrier has a plurality of through holes, a carrying surface, and a back surface corresponding to the carrying surface. The back surface has a plurality of contacts around the through holes. The chip with an active surface and a plurality of bonding pads on the active surface is disposed on the carrying surface. The active surface is attached to the carrying surface and the through holes expose the bonding pads. The bonding wires go through the through holes to electrically connect with the bonding pads and the contacts. In addition, the shape and size of the molding compound can be adjusted for covering the chip, the contacts, and the bonding wires.

摘要翻译： 提供了包括载体，芯片，多个接合线和模塑料的通用芯片封装结构。 载体具有多个通孔，承载表面和对应于承载表面的后表面。 后表面具有围绕通孔的多个触点。 具有活性表面的芯片和有源表面上的多个接合焊盘设置在承载表面上。 活性表面附着在承载表面上，通孔露出接合垫。 接合线穿过通孔，以与接合焊盘和触点电连接。 此外，可以调整模塑料的形状和尺寸以覆盖芯片，触点和接合线。

公开(公告)号：USRE42349E1

公开(公告)日：2011-05-10

申请号：US11371307

申请日：2006-03-07

申请人： Chun-Hung Lin ,  Jesse Huang ,  Kuang-Hui Chen ,  Shih-Wen Chou

发明人： Chun-Hung Lin ,  Jesse Huang ,  Kuang-Hui Chen ,  Shih-Wen Chou

IPC分类号： B05D5/10 ,  B05D3/12 ,  H01L21/00

CPC分类号： H01L24/27 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49513 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/05599 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/274 ,  H01L2224/29101 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/484 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/85399 ,  H01L2224/92147 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

摘要： A wafer treating method for making adhesive dies is provided. A liquid adhesive with two-stage property is coated on a surface of a wafer. Then, the wafer is pre-cured to make the liquid adhesive transform a thermo-bonding adhesive film having B-stage property which has a glass transition temperature not less than 40° C. for handling without adhesive under room temperature. After positioning the wafer, the wafer is singulated to form a plurality of dies with adhesive for die-to-die stacking, die-to-substrate or die-to-leadframe attaching.

摘要翻译： 提供了一种用于制造粘合剂模具的晶片处理方法。 具有两级特性的液体粘合剂涂覆在晶片的表面上。 然后，将晶片预固化，使液体粘合剂转变具有玻璃化转变温度不低于40℃的B阶特性的热粘合粘合剂膜，以在室温下无粘合剂进行处理。 在定位晶片之后，将晶片单片化以形成具有用于管芯到管芯堆叠，管芯到衬底或管芯到引线框架附接的粘合剂的多个管芯。

公开(公告)号：US20100123234A1

公开(公告)日：2010-05-20

申请号：US12350966

申请日：2009-01-09

申请人： Shih-Wen Chou

发明人： Shih-Wen Chou

IPC分类号： H01L23/00 ,  H01L21/50

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L25/0652 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A multi-chip package includes a carrier, a first chip, a relay circuit substrate, a number of first bonding wires, a number of second bonding wires, a second chip, a number of third bonding wires, and an adhesive layer. The first chip is disposed on the carrier. The relay circuit substrate is disposed on the first chip. The first bonding wires are electrically connected between the first chip and the relay circuit substrate. The second bonding wires are electrically connected between the relay circuit substrate and the carrier. The second chip is disposed on the carrier and is stacked with the first chip. The third bonding wires are electrically connected between the second chip and the carrier. The adhesive layer is adhered between the first chip and the second chip. In addition, a manufacturing method of a multi-chip package is also provided.

摘要翻译： 多芯片封装包括载体，第一芯片，中继电路基板，多个第一接合线，多个第二接合线，第二芯片，多个第三接合线和粘合剂层。 第一芯片设置在载体上。 继电器电路基板设置在第一芯片上。 第一接合线电连接在第一芯片和继电器电路基板之间。 第二接合线电连接在继电器电路基板和载体之间。 第二芯片设置在载体上并与第一芯片堆叠。 第三接合线电连接在第二芯片和载体之间。 粘合剂层粘附在第一芯片和第二芯片之间。 此外，还提供了一种多芯片封装的制造方法。