公开(公告)号：US20070122998A1

公开(公告)日：2007-05-31

申请号：US11698558

申请日：2007-01-26

申请人： Steve Droes ,  Masao Moriguchi ,  Yutaka Takafuji

发明人： Steve Droes ,  Masao Moriguchi ,  Yutaka Takafuji

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/76254 ,  H01L27/1266 ,  H01L29/78603

摘要： A system and method for hydrogen (H) exfoliation are provided for attaching silicon-on-insulator (SOI) fabricated circuits to carrier substrates. The method comprises: providing a SOI substrate, including a silicon (Si) active layer and buried oxide (BOX) layer overlying a Si substrate; forming a circuit in the Si active layer; forming a blocking mask over selected circuit areas; implanting H in the Si substrate; annealing; removing the blocking mask; in response to the H implanting, forming a cleaving plane in the Si substrate; bonding the circuit the top oxide layer to the carrier substrate; and, cleaving the Si substrate. More specifically, the cleaving plane is formed along a horizontal peak concentration (Rp) H layer in the Si substrate and along the buried oxide layer interface.

摘要翻译： 提供氢（H）剥离的系统和方法用于将绝缘体上硅（SOI）制造的电路附着到载体衬底上。 该方法包括：提供SOI衬底，其包括覆盖在Si衬底上的硅（Si）有源层和掩埋氧化物（BOX）层; 在Si有源层中形成电路; 在选定的电路区域上形成阻挡掩模; 在Si衬底中注入H; 退火; 去除阻挡掩模; 响应于H植入，在Si衬底中形成切割平面; 将电路的顶部氧化物层接合到载体衬底; 并切割Si衬底。 更具体地说，切割平面沿着Si衬底中的水平峰值浓度（Rp）H层并且沿掩埋氧化物层界面形成。

公开(公告)号：US20060068565A1

公开(公告)日：2006-03-30

申请号：US10953938

申请日：2004-09-28

申请人： Steve Droes ,  Masao Moriguchi ,  Yutaka Takafuji

发明人： Steve Droes ,  Masao Moriguchi ,  Yutaka Takafuji

IPC分类号： H01L21/44

CPC分类号： H01L21/76254 ,  H01L27/1266 ,  H01L29/78603

摘要： A system and method for hydrogen (H) exfoliation are provided for attaching silicon-on-insulator (SOI) fabricated circuits to carrier substrates. The method comprises: providing a SOI substrate, including a silicon (Si) active layer and buried oxide (BOX) layer overlying a Si substrate; forming a circuit in the Si active layer; forming a blocking mask over selected circuit areas; implanting H in the Si substrate; annealing; removing the blocking mask; in response to the H implanting, forming a cleaving plane in the Si substrate; bonding the circuit the top oxide layer to the carrier substrate; and, cleaving the Si substrate. More specifically, the cleaving plane is formed along a horizontal peak concentration (Rp) H layer in the Si substrate and along the buried oxide layer interface.

摘要翻译： 提供氢（H）剥离的系统和方法用于将绝缘体上硅（SOI）制造的电路附着到载体衬底上。 该方法包括：提供SOI衬底，其包括覆盖在Si衬底上的硅（Si）有源层和掩埋氧化物（BOX）层; 在Si有源层中形成电路; 在选定的电路区域上形成阻挡掩模; 在Si衬底中注入H; 退火; 去除阻挡掩模; 响应于H植入，在Si衬底中形成切割平面; 将电路的顶部氧化物层接合到载体衬底; 并切割Si衬底。 更具体地说，切割平面沿着Si衬底中的水平峰值浓度（Rp）H层并且沿掩埋氧化物层界面形成。

公开(公告)号：US20050236626A1

公开(公告)日：2005-10-27

申请号：US11088252

申请日：2005-03-24

申请人： Yutaka Takafuji ,  Takashi Itoga ,  Steven Droes ,  Masao Moriguchi

发明人： Yutaka Takafuji ,  Takashi Itoga ,  Steven Droes ,  Masao Moriguchi

IPC分类号： G02F1/1368 ,  H01L21/00 ,  H01L21/02 ,  H01L21/265 ,  H01L21/336 ,  H01L21/58 ,  H01L21/60 ,  H01L21/68 ,  H01L21/77 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L27/32 ,  H01L29/04 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L51/56

CPC分类号： H01L24/83 ,  H01L21/6835 ,  H01L24/24 ,  H01L24/26 ,  H01L24/82 ,  H01L27/1214 ,  H01L27/1266 ,  H01L27/3241 ,  H01L29/66765 ,  H01L29/66772 ,  H01L29/78603 ,  H01L51/56 ,  H01L2221/68363 ,  H01L2224/24226 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/00

摘要： In a semiconductor device including an insulative substrate and a thin film device formed thereon, a thin film transistor having a non-single crystalline silicon thin film and a transistor having a single crystalline silicon thin film are intermixed, and a gate electrode film of the thin film transistor having single crystalline silicon is made of a material including a metal whose mass number is larger than that of silicon or a compound containing the metal.

摘要翻译： 在包括绝缘性基板和形成在其上的薄膜器件的半导体器件中，将具有非单晶硅薄膜的薄膜晶体管和具有单晶硅薄膜的晶体管混合，并且将薄的薄膜晶体管 具有单晶硅的薄膜晶体管由包括质量数大于硅的金属或含有金属的化合物的材料制成。

公开(公告)号：US07179719B2

公开(公告)日：2007-02-20

申请号：US10953938

申请日：2004-09-28

申请人： Steve Droes ,  Masao Moriguchi ,  Yutaka Takafuji

发明人： Steve Droes ,  Masao Moriguchi ,  Yutaka Takafuji

IPC分类号： H01L21/46 ,  H01L21/30

CPC分类号： H01L21/76254 ,  H01L27/1266 ,  H01L29/78603

摘要： A system and method for hydrogen (H) exfoliation are provided for attaching silicon-on-insulator (SOI) fabricated circuits to carrier substrates. The method comprises: providing a SOI substrate, including a silicon (Si) active layer and buried oxide (BOX) layer overlying a Si substrate; forming a circuit in the Si active layer; forming a blocking mask over selected circuit areas; implanting H in the Si substrate; annealing; removing the blocking mask; in response to the H implanting, forming a cleaving plane in the Si substrate; bonding the circuit the top oxide layer to the carrier substrate; and, cleaving the Si substrate. More specifically, the cleaving plane is formed along a horizontal peak concentration (Rp) H layer in the Si substrate and along the buried oxide layer interface.

摘要翻译： 提供氢（H）剥离的系统和方法用于将绝缘体上硅（SOI）制造的电路附着到载体衬底上。 该方法包括：提供SOI衬底，其包括覆盖在Si衬底上的硅（Si）有源层和掩埋氧化物（BOX）层; 在Si有源层中形成电路; 在选定的电路区域上形成阻挡掩模; 在Si衬底中注入H; 退火; 去除阻挡掩模; 响应于H植入，在Si衬底中形成切割平面; 将电路的顶部氧化物层接合到载体衬底; 并切割Si衬底。 更具体地说，切割平面沿着Si衬底中的水平峰值浓度（Rp）H层并且沿掩埋氧化物层界面形成。

公开(公告)号：US07897443B2

公开(公告)日：2011-03-01

申请号：US11883483

申请日：2006-01-17

申请人： Masao Moriguchi ,  Yutaka Takafuji ,  Steven Roy Droes

发明人： Masao Moriguchi ,  Yutaka Takafuji ,  Steven Roy Droes

IPC分类号： H01L21/762

CPC分类号： H01L27/1266 ,  H01L21/76243 ,  H01L21/76256 ,  H01L27/1214 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833

摘要： The present invention provides a production method of a semiconductor device, which can improve characteristics of a semiconductor element including a single crystal semiconductor layer formed by transferring on an insulating substrate. The present invention is a production method of a semiconductor device comprising a single crystal semiconductor layer formed on an insulating substrate, the production method comprising the steps of: implanting a substance for separation into a single crystal semiconductor substrate, thereby forming a separation layer; transferring a part of the single crystal semiconductor substrate, separated at the separation layer, onto the insulating substrate, thereby forming the single crystal semiconductor layer; forming a hydrogen-containing layer on at least one side of the single crystal semiconductor layer; and diffusing hydrogen from the hydrogen-containing layer to the single crystal semiconductor layer.

摘要翻译： 本发明提供一种半导体器件的制造方法，其能够提高包含通过在绝缘基板上转印而形成的单晶半导体层的半导体元件的特性。 本发明是一种半导体器件的制造方法，其包括在绝缘基板上形成的单晶半导体层，其制造方法包括以下步骤：将分离用物质注入单晶半导体基板，形成分离层; 将在分离层分离的单晶半导体衬底的一部分转印到绝缘衬底上，从而形成单晶半导体层; 在所述单晶半导体层的至少一侧上形成含氢层; 并将氢从含氢层扩散到单晶半导体层。

公开(公告)号：US08884297B2

公开(公告)日：2014-11-11

申请号：US13696865

申请日：2011-05-06

申请人： Sachiaki Tezuka ,  Yasuhiro Jinbo ,  Toshinari Sasaki ,  Hidekazu Miyairi ,  Yosuke Kanzaki ,  Masao Moriguchi

发明人： Sachiaki Tezuka ,  Yasuhiro Jinbo ,  Toshinari Sasaki ,  Hidekazu Miyairi ,  Yosuke Kanzaki ,  Masao Moriguchi

IPC分类号： H01L21/336 ,  H01L21/205 ,  H01L29/04 ,  H01L29/786 ,  H01L21/02 ,  C23C16/50 ,  C23C16/455 ,  C23C16/24 ,  H01L29/66

CPC分类号： H01L21/02513 ,  C23C16/24 ,  C23C16/45523 ,  C23C16/50 ,  H01L21/02422 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78696

摘要： A manufacturing method of a microcrystalline silicon film includes the steps of forming a first microcrystalline silicon film over an insulating film by a plasma CVD method under a first condition; and forming a second microcrystalline silicon film over the first microcrystalline silicon film under a second condition. As a source gas supplied to a treatment chamber, a deposition gas containing silicon and a gas containing hydrogen are used. In the first condition, a flow rate of hydrogen is set at a flow rate 50 to 1000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 67 to 1333 Pa inclusive. In the second condition, a flow rate of hydrogen is set at a flow rate 100 to 2000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 1333 to 13332 Pa inclusive.

摘要翻译： 微晶硅膜的制造方法包括以下步骤：在第一条件下通过等离子体CVD法在绝缘膜上形成第一微晶硅膜; 以及在第二条件下在所述第一微晶硅膜上形成第二微晶硅膜。 作为供给到处理室的源气体，使用含有硅和含氢气体的沉积气体。 在第一条件下，将氢的流量设定为包含沉积气体的流量的50〜1000倍，处理室内的压力为67〜1333Pa。 在第二条件下，将氢的流量设定为包含沉积气体的流量的100〜2000倍，处理室内的压力为1333〜13332Pa。

公开(公告)号：US20140103342A1

公开(公告)日：2014-04-17

申请号：US14124178

申请日：2012-05-29

申请人： Yudai Takanishi ,  Masao Moriguchi ,  Yohsuke Kanzaki ,  Takatsugu Kusumi

发明人： Yudai Takanishi ,  Masao Moriguchi ,  Yohsuke Kanzaki ,  Takatsugu Kusumi

IPC分类号： H01L29/786 ,  H01L29/66

CPC分类号： H01L29/78606 ,  H01L27/1225 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869

摘要： A method of manufacturing a TFT substrate includes: forming a gate electrode (12) and a gate insulating film (30) on a substrate (8); forming a source electrode (14) and a drain electrode (15) at a gap from each other on the gate insulating film (30), and forming a drain connection part (16); forming, after the step of forming the source electrode and the drain electrode, an oxide semiconductor layer (18, 18a, 18b) that contains a channel portion connecting the source electrode (14) to the drain electrode (15) and that contains an additional portion (18a) covering the drain connection part (16); oxidizing a surface of the oxide semiconductor layer (18, 18a, 18b); forming a contact hole (22) in an insulating film (32) that covers the oxide semiconductor layer; removing a portion of the additional portion (18a) of the oxide semiconductor layer that is located inside the contact hole (22); and forming a conductive layer (20) that electrically connects the drain connection part (16) that has been exposed.

摘要翻译： 制造TFT基板的方法包括：在基板（8）上形成栅极（12）和栅极绝缘膜（30）; 在所述栅极绝缘膜（30）上形成彼此间隔开的源极（14）和漏极（15），形成漏极连接部（16）。 在形成所述源电极和所述漏电极的步骤之后，形成包含将所述源电极（14）连接到所述漏电极（15）的沟道部分的氧化物半导体层（18,18a，18b），所述沟道部分包含附加 （18a）覆盖所述排水连接部（16）。 氧化氧化物半导体层（18,18a，18b）的表面; 在覆盖氧化物半导体层的绝缘膜（32）中形成接触孔（22）; 去除位于接触孔（22）内的氧化物半导体层的附加部分（18a）的一部分; 以及形成电连接已经暴露的漏极连接部分（16）的导电层（20）。

公开(公告)号：US20130026574A1

公开(公告)日：2013-01-31

申请号：US13639122

申请日：2011-01-25

申请人： Kenji Nakanishi ,  Masao Moriguchi ,  Atsuyuki Hoshino

发明人： Kenji Nakanishi ,  Masao Moriguchi ,  Atsuyuki Hoshino

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/78618 ,  G02F1/1362 ,  H01L29/66765 ,  H01L29/78669 ,  H01L29/78678

摘要： In an inverted staggered type TFT (100), contact layers (150a and 150b) that electrically connect a channel layer (140) to source and drain electrodes (160a and 160b), respectively, include n+ amorphous silicon layers (151a and 151b), n+ microcrystalline silicon layers (152a and 152b), and n+ microcrystalline silicon layers (153a and 153b). The n+ microcrystalline silicon layers (152a and 152b) have a lower crystallization rate than the n+ microcrystalline silicon layers (153a and 153b) and are formed between the n+ amorphous silicon layers (151a and 151b) and the n+ microcrystalline silicon layers (153a and 153b). In this case, since the film thickness of incubation layers formed on surfaces of the n+ amorphous silicon layers (151a and 151b) decreases, the resistance value of the contact layers (150a and 150b) decreases. By this, the contact resistance of the TFT (100) decreases and the mobility can be increased.

摘要翻译： 在倒置交错型TFT（100）中，分别将沟道层（140）与源极和漏极电极（160a和160b）电连接的接触层（150a和150b）包括n +非晶硅层（151a和151b） n +微晶硅层（152a和152b）和n +微晶硅层（153a和153b）。 n +微晶硅层（152a和152b）具有比n +微晶硅层（153a和153b）更低的结晶速率，并且形成在n +非晶硅层（151a和151b）与n +微晶硅层（153a和153b）之间 ）。 在这种情况下，由于形成在n +非晶硅层（151a，151b）的表面上的温育层的膜厚减小，所以接触层（150a，150b）的电阻值降低。 由此，TFT（100）的接触电阻降低，并且可以提高迁移率。

公开(公告)号：US20110303916A1

公开(公告)日：2011-12-15

申请号：US13147640

申请日：2010-01-29

申请人： Yudai Takanishi ,  Masao Moriguchi

发明人： Yudai Takanishi ,  Masao Moriguchi

IPC分类号： H01L29/786

CPC分类号： H01L27/124 ,  H01L29/41733

摘要： A semiconductor device of the present invention includes: a lower electrode (110); a contact layer (130) including a first contact layer (132), a second contact layer (134) and a third contact layer (136) overlapping with a semiconductor layer (120); and an upper electrode (140) including a first upper electrode (142), a second upper electrode (144) and a third upper electrode (146). The second contact layer (134) includes a first region (134a), and a second region (134b) separate from the first region (134a), and the second upper electrode (144) is directly in contact with the semiconductor layer (120) in a region between the first region (134a) and the second region (134b) of the second contact layer (134).

摘要翻译： 本发明的半导体器件包括：下电极（110）; 包括与半导体层（120）重叠的第一接触层（132），第二接触层（134）和第三接触层（136）的接触层（130）; 和包括第一上电极（142），第二上电极（144）和第三上电极（146）的上电极（140）。 第二接触层（134）包括第一区域（134a）和与第一区域（134a）分离的第二区域（134b），第二上部电极（144）直接与半导体层（120）接触， 在第二接触层（134）的第一区域（134a）和第二区域（134b）之间的区域中。

公开(公告)号：US20150108467A1

公开(公告)日：2015-04-23

申请号：US13996033

申请日：2011-12-15

申请人： Masao Moriguchi ,  Yohsuke Kanzaki ,  Yudai Takanishi ,  Takatsugu Kusumi ,  Hiroshi Matsukizono

发明人： Masao Moriguchi ,  Yohsuke Kanzaki ,  Yudai Takanishi ,  Takatsugu Kusumi ,  Hiroshi Matsukizono

IPC分类号： H01L23/00 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L27/124 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134372 ,  H01L23/564 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device (100) according to the present invention is a semiconductor device with a thin-film transistor (10), and includes: a gate electrode (62) which has been formed on a substrate (60) as a part of the thin-film transistor (10); a gate insulating layer (66) which has been formed on the gate electrode (62); an oxide semiconductor layer (68) which has been formed on the gate insulating layer (66); a source electrode (70s) and a drain electrode (70d) which have been formed on the oxide semiconductor layer (68); a protective layer (72) which has been formed on the oxide semiconductor layer (68), the source electrode (70s) and the drain electrode (70d); an oxygen supplying layer (74) which has been formed on the protective layer (72); and an anti-diffusion layer (78) which has been formed on the oxygen supplying layer (74).

摘要翻译： 根据本发明的半导体器件（100）是具有薄膜晶体管（10）的半导体器件，包括：栅极电极（62），其形成在基板（60）上，作为薄膜晶体管 - 薄膜晶体管（10）; 已经形成在所述栅极（62）上的栅极绝缘层（66）; 形成在栅极绝缘层（66）上的氧化物半导体层（68）; 形成在所述氧化物半导体层上的源极电极和漏极电极， 形成在氧化物半导体层（68）上的保护层（72），源电极（70s）和漏电极（70d）。 形成在保护层（72）上的供氧层（74）; 和形成在供氧层（74）上的抗扩散层（78）。