公开(公告)号：US20090218620A1

公开(公告)日：2009-09-03

申请号：US12074087

申请日：2008-02-28

申请人： Francois Hebert ,  Anup Bhalla

发明人： Francois Hebert ,  Anup Bhalla

IPC分类号： H01L29/78 ,  H01L21/20

CPC分类号： H01L29/7802 ,  H01L24/05 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/7803 ,  H01L2224/0603 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

摘要： This invention discloses a semiconductor power device disposed on a semiconductor substrate supporting an epitaxial layer as a drift region composed of an epitaxial layer. The semiconductor power device further includes a super-junction structure includes a plurality of doped sidewall columns disposed in a multiple of epitaxial layers. The epitaxial layer have a plurality of trenches opened and filled with the multiple epitaxial layer therein with the doped columns disposed along sidewalls of the trenches disposed in the multiple of epitaxial layers.

摘要翻译： 本发明公开了一种半导体功率器件，其设置在支撑外延层的半导体衬底上，作为由外延层构成的漂移区。 半导体功率器件还包括超结结构，其包括设置在多个外延层中的多个掺杂侧壁。 外延层具有多个沟槽，其中多个外延层开放并填充，其中掺杂的列沿着设置在多个外延层中的沟槽的侧壁设置。

公开(公告)号：US07557554B2

公开(公告)日：2009-07-07

申请号：US11861154

申请日：2007-09-25

申请人： Yu Cheng Chang

发明人： Yu Cheng Chang

IPC分类号： G05F1/575 ,  G05F1/618

CPC分类号： H02M3/1588 ,  H02M3/157 ,  Y02B70/1466

摘要： A voltage/current control apparatus and method are disclosed. The apparatus includes a low-side field effect transistor (FET) having a source, a gate and a drain, a high-side field effect transistor (FET) having a source, a gate and a drain, a gate driver integrated circuit (IC), a sample and hold circuit, and a comparator configured to produce a trigger signal at the output when a sum of the first and second input signals is equal to a sum of the third and fourth input signals, wherein the trigger signal is configured to trigger a beginning of a new cycle by turning the gate of the high-side FET “on” and the gate of the low-side FET “off”.

摘要翻译： 公开了电压/电流控制装置和方法。 该装置包括具有源极，栅极和漏极的低侧场效应晶体管（FET），具有源极，栅极和漏极的高侧场效应晶体管（FET），栅极驱动器集成电路（IC ），采样保持电路和比较器，被配置为当第一和第二输入信号的和等于第三和第四输入信号的和时在输出端产生触发信号，其中触发信号被配置为 通过使高侧FET的栅极“开”并且低边FET的栅极“关闭”来触发新周期的开始。

公开(公告)号：US07554154B2

公开(公告)日：2009-06-30

申请号：US11495803

申请日：2006-07-28

申请人： François Hébert

发明人： François Hébert

IPC分类号： H01L29/76

CPC分类号： H01L29/4175 ,  H01L21/26513 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

摘要： This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region. The combined sinker-channel region extending below the drift region and the combined sinker-channel region that has a dopant-conductivity opposite to and compensating the drift region for reducing the source-drain capacitance.

摘要翻译： 本发明公开了底源横向扩散MOS（BS-LDMOS）器件。 器件具有在半导体衬底的顶表面附近的漏区附近设置的源极区域，该半导体衬底在源极区域和漏极区域之间支撑栅极。 BS-LDMOS器件还具有一个组合的沉降通道区域，该半导体衬底的深度完全位于靠近顶表面的源极区域附近设置的体区域之下，其中组合沉降通道区域用作掩埋源体 用于将主体区域和源区域电连接到用作源电极的衬底的底部。 漂移区域设置在栅极下方的顶表面附近并且远离源极区域并且延伸到并包围漏极区域。 在漂移区域下方延伸的组合沉降通道区域和具有与掺杂剂 - 导电性相反并补偿漂移区域以减少源极 - 漏极电容的组合沉降沟道区域。

公开(公告)号：US20090072301A1

公开(公告)日：2009-03-19

申请号：US12313305

申请日：2008-11-18

申请人： Anup Bhalla ,  Sik K. Lui

发明人： Anup Bhalla ,  Sik K. Lui

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811

摘要： This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one active cell further includes a trenched source contact opened between the trenches wherein the trenched source contact opened through a source region into a body region for electrically connecting the source region to a source metal disposed on top of an insulation layer wherein a trench bottom surface of the trenched source contact further covered with a conductive material to function as an integrated Schottky barrier diode in said active cell. A shielding structure is disposed at the bottom and insulated from the trenched gate to provide shielding effect for both the trenched gate and the Schottky diode.

摘要翻译： 本发明公开了一种半导体功率器件，其包括由在半导体衬底中开口的沟槽围绕的多个功率晶体管单元。 至少一个有源电池还包括在沟槽之间开放的沟槽的源极触点，其中沟槽的源极触点通过源极区域开放到主体区域中，用于将源区域电连接到设置在绝缘层顶部的源极金属，其中沟槽底部 沟槽源极接触表面进一步用导电材料覆盖，以用作所述活性电池中的集成肖特基势垒二极管。 屏蔽结构设置在底部并与沟槽栅绝缘，以为沟槽栅极和肖特基二极管提供屏蔽效应。

公开(公告)号：US07492005B2

公开(公告)日：2009-02-17

申请号：US11321957

申请日：2005-12-28

申请人： Hong Chang ,  Sung-Shan Tai ,  Tiesheng Li ,  Yu Wang

发明人： Hong Chang ,  Sung-Shan Tai ,  Tiesheng Li ,  Yu Wang

IPC分类号： H01L29/76

CPC分类号： H01L21/76232 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/7834

摘要： This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a shielded gate trench (SGT) structure below and insulated from the trenched gate. The SGT structure is formed substantially as a round hole having a lateral expansion extended beyond the trench gate and covered by a dielectric liner layer filled with a trenched gate material. The round hole is formed by an isotropic etch at the bottom of the trenched gate and is insulated from the trenched gate by an oxide insulation layer. The round hole has a lateral expansion beyond the trench walls and the lateral expansion serves as a vertical alignment landmark for controlling the depth of the trenched gate. The MOSFET device has a reduced gate to drain capacitance Cgd depending on the controllable depth of the trenched gate disposed above the SGT structure formed as a round hole below the trenched gate.

摘要翻译： 本发明公开了一种改进的沟槽金属氧化物半导体场效应晶体管（MOSFET）器件，其包括被包围在设置在衬底的底表面上的漏区以上的体区中的源极区包围的沟槽栅极。 MOSFET单元进一步包括屏蔽栅极沟槽（SGT）结构，并且与沟槽栅极绝缘。 SGT结构基本上形成为具有延伸超过沟槽栅极并且被填充有沟槽栅极材料的介电衬垫层覆盖的横向膨胀的圆孔。 圆形孔通过在沟槽底部的各向同性蚀刻形成，并且通过氧化物绝缘层与沟槽栅极绝缘。 圆孔具有超出沟槽壁的横向膨胀，并且横向膨胀用作用于控制沟槽浇口的深度的垂直对准界标。 MOSFET器件具有减小的栅极到漏极电容Cgd，这取决于设置在形成为沟槽栅极下方的圆孔的SGT结构之上的沟槽栅极的可控深度。

公开(公告)号：US20080310065A1

公开(公告)日：2008-12-18

申请号：US12080104

申请日：2008-04-01

申请人： Moses Ho ,  Madhur Bobde ,  Mike Chang ,  Limin Weng

发明人： Moses Ho ,  Madhur Bobde ,  Mike Chang ,  Limin Weng

IPC分类号： H02H9/04

CPC分类号： H01L27/0676 ,  H01L23/552 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transient voltage suppressing (TVS) circuit with uni-directional blocking and symmetric bi-directional blocking capabilities integrated with an electromagnetic interference (EMI) filter supported on a semiconductor substrate of a first conductivity type. The TVS circuit integrated with the EMI filter further includes a ground terminal disposed on the surface for the symmetric bi-directional blocking structure and at the bottom of the semiconductor substrate for the uni-directional blocking structure and an input and an output terminal disposed on a top surface with at least a Zener diode and a plurality of capacitors disposed in the semiconductor substrate to couple the ground terminal to the input and output terminals with a direct capacitive coupling without an intermediate floating body region.

摘要翻译： 具有与第一导电类型的半导体衬底上支持的电磁干扰（EMI）滤波器集成的具有单向阻塞和对称双向阻塞能力的瞬态电压抑制（TVS）电路。 与EMI滤波器集成的TVS电路还包括设置在用于对称双向阻塞结构的表面上的接地端子和用于单向阻塞结构的半导体衬底的底部以及设置在单向阻断结构上的输入和输出端子 具有至少齐纳二极管的顶表面和设置在半导体衬底中的多个电容器，以将接地端子连接到具有直接电容耦合而不具有中间浮体区域的输入和输出端子。

公开(公告)号：US20080304306A1

公开(公告)日：2008-12-11

申请号：US11761313

申请日：2007-06-11

申请人： Allen Chang ,  Wai-Keung Peter Cheng

发明人： Allen Chang ,  Wai-Keung Peter Cheng

IPC分类号： H02M3/02 ,  H02M1/00

CPC分类号： H01L25/16 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/13091 ,  H02M3/155 ,  H02M7/003 ,  H01L2924/00

摘要： A high voltage and high power boost converter is disclosed. The boost converter includes a boost converter IC and a discrete Schottky diode, both of which are co-packaged on a standard single common die pad.

摘要翻译： 公开了一种高压和高功率升压转换器。 升压转换器包括升压转换器IC和离散肖特基二极管，它们都被共同封装在标准的单个公共管芯焊盘上。

公开(公告)号：US20080296673A1

公开(公告)日：2008-12-04

申请号：US11807444

申请日：2007-05-29

申请人： Sung-Shan Tai ,  Yongzhong Hu

发明人： Sung-Shan Tai ,  Yongzhong Hu

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734

摘要： This invention discloses a trenched semiconductor power device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments with a bottom insulation layer surrounding a bottom trench-filling segment having a bird-beak shaped layer on a top portion of the bottom insulation attached to sidewalls of the trench extending above a top surface of the bottom trench-filling segment.

摘要翻译： 本发明公开了一种沟槽半导体功率器件，其包括被包围在设置在衬底的底表面上的漏区以上的体区中的源极区围绕的沟槽栅极。 沟槽栅极还包括至少两个相互绝缘的沟槽填充段，其中底部绝缘层围绕底部沟槽填充段，底部沟槽填充段在底部绝缘体的顶部附近具有鸟嘴形层，其附着于沟槽的侧壁， 底部沟槽填充段的顶表面。

公开(公告)号：US20080265312A1

公开(公告)日：2008-10-30

申请号：US12217092

申请日：2008-06-30

申请人： Anup Bhalla ,  Xiaobin Wang ,  Moses Ho

发明人： Anup Bhalla ,  Xiaobin Wang ,  Moses Ho

IPC分类号： H01L27/06 ,  H01L21/8234

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/872

摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.

摘要翻译： 本发明公开了一种包括具有多个功率晶体管单元的有源单元区域的半导体功率器件。 每个所述功率晶体管单元具有平面肖特基二极管，其包括覆盖两个相邻功率晶体管单元之间的分离体区域之间的间隙上方的区域的肖特基结阻挡金属。 分离体区域还提供调节每个所述功率晶体管单元中的所述肖特基二极管的漏电流的功能。 每个平面肖特基二极管还包括设置在两个相邻功率晶体管单元的分离的体区之间的间隙中的香农注入区，用于进一步调整所述肖特基二极管的漏电流。 每个功率晶体管单元进一步包括分离体区域中的重体掺杂区域，其邻近形成结屏障肖特基（JBS）口袋区域的围绕所述肖特基二极管的源极区域。

公开(公告)号：US20080173969A1

公开(公告)日：2008-07-24

申请号：US11656104

申请日：2007-01-22

申请人： Francois Hebert ,  Tao Feng

发明人： Francois Hebert ,  Tao Feng

IPC分类号： H01L29/423 ,  H01L21/28

CPC分类号： H01L29/7802 ,  H01L29/0653 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7803 ,  H01L29/861 ,  H01L29/872

摘要： This invention discloses semiconductor device that includes a top region and a bottom region with an intermediate region disposed between said top region and said bottom region with a controllable current path traversing through the intermediate region. The semiconductor device further includes a trench with padded with insulation layer on sidewalls extended from the top region through the intermediate region toward the bottom region wherein the trench includes randomly and substantially uniformly distributed nano-nodules as charge-islands in contact with a drain region below the trench for electrically coupling with the intermediate region for continuously and uniformly distributing a voltage drop through the current path.

摘要翻译： 本发明公开了一种半导体器件，其包括顶部区域和底部区域，其中间区域设置在所述顶部区域和所述底部区域之间，并具有穿过所述中间区域的可控电流通路。 所述半导体器件还包括沟槽，该沟槽在从所述顶部区域延伸穿过所述中间区域朝向所述底部区域的侧壁上被填充有绝缘层，其中所述沟槽包括随机均匀分布的纳米结节，作为与下面的漏极区域接触的电荷岛 用于与中间区域电耦合的沟槽，用于通过电流路径连续均匀地分配电压降。