公开(公告)号：US09478625B1

公开(公告)日：2016-10-25

申请号：US14878440

申请日：2015-10-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi ,  Huang Liu

IPC: H01L21/00 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/43 ,  H01L21/8234 ,  H01L21/324 ,  H01L21/265 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823443 ,  H01L27/0629 ,  H01L28/24 ,  H01L29/66545

Abstract: A semiconductor structure includes a semiconductor substrate, fins coupled to the substrate and surrounded at a bottom portion thereof by isolation material, and resistor(s) situated in the gate region(s), the gate regions being filled with undoped dummy gate material. As part of a replacement gate process, the resistor(s) are realized by forming silicide over dummy gate material, i.e., the dummy gate material for the resistor(s) is not removed.

Abstract translation: 半导体结构包括：半导体衬底，耦合到衬底并且在其底部被隔离材料包围的鳍片以及位于栅极区域中的电阻器，栅极区域被未掺杂的虚拟栅极材料填充。 作为替代栅极处理的一部分，通过在伪栅极材料上形成硅化物，即不去除用于电阻器的虚拟栅极材料来实现电阻器。

公开(公告)号：US09472574B2

公开(公告)日：2016-10-18

申请号：US14609115

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang

IPC: H01L27/12 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: For fabrication of a semiconductor structure, there is set forth herein a method of fabricating a semiconductor structure, the method including forming a multilayer structure, the multilayer structure having a bulk substrate, a first layer defining an ultrathin body spaced apart from the bulk substrate, and a second layer above the first layer having material for defining a fin, and patterning the second layer to define a fin above the ultrathin body.

Abstract translation: 为了制造半导体结构，这里提出了一种制造半导体结构的方法，该方法包括形成多层结构，该多层结构具有体基片，限定与本体衬底间隔开的超薄体的第一层， 并且在第一层之上的第二层具有用于限定翅片的材料，并且图案化第二层以限定超薄体上方的翅片。

公开(公告)号：US09472572B2

公开(公告)日：2016-10-18

申请号：US14270833

申请日：2014-05-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/088 ,  H01L27/092 ,  H01L29/165

CPC classification number: H01L27/1211 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

Abstract: Approaches for simultaneously providing a set of merged and unmerged fins in a fin field effect transistor device (FinFET) are disclosed. In at least one approach, the FinFET device includes: a set of merged fins and a set of unmerged fins formed from a substrate, the set of unmerged fins adjacent the set of merged fins; and a planar block formed from the substrate, the planar block adjacent one of: the set of merged fins, and the set of unmerged fins. The FinFET device further includes an epitaxial material over each of the set of merged fins and each of the set of unmerged fins, wherein the epitaxial material merges together over the set of merged fins and remains unmerged over the set of unmerged fins. In at least one approach, the set of merged fins and the set of unmerged fins is formed using a sidewall image transfer process.

Abstract translation: 公开了在翅片场效应晶体管器件（FinFET）中同时提供一组合并和非鳍片的方法。 在至少一种方法中，FinFET器件包括：一组合并的散热片和一组从衬底形成的未成形翅片，所述一组未合并的散热片邻近该组合的翅片; 以及由该基板形成的平面块，该平面块相邻于一组合并翅片，以及一组未熔合翼片。 FinFET器件还包括在所述一组合并的散热片中的每一个上的外延材料和所述一组未熔合的翅片中的每一个，其中所述外延材料在所述一组合并的翅片上合并在一起，并且保持未被覆盖在所述一组未熔合的翅片上。 在至少一种方法中，使用侧壁图像转印处理形成所述组合的散热片和所述一组未成形散热片。

公开(公告)号：US09443738B2

公开(公告)日：2016-09-13

申请号：US14616226

申请日：2015-02-06

Applicant: GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hui Zang ,  Balasubramanian Pranatharthiharan

IPC: H01L29/78 ,  H01L21/283 ,  H01L21/28

CPC classification number: H01L21/76897 ,  H01L29/66545

Abstract: Semiconductor devices and methods for forming the devices with middle of line capacitance reduction in self-aligned contact process flow are provided. One method includes, for instance: obtaining a wafer with at least one source, at least one drain, and at least one sacrificial gate; forming a first contact region over the at least one source and a second contact region over the at least one drain; removing the at least one sacrificial gate; forming at least one gate; and forming at least one small contact over the first contact region and the second contact region. An intermediate semiconductor device is also disclosed.

Abstract translation: 提供了用于形成具有自对准接触工艺流程中线路电容减小的器件的半导体器件和方法。 一种方法包括，例如：获得具有至少一个源，至少一个漏极和至少一个牺牲栅极的晶片; 在所述至少一个源极上形成第一接触区域，以及在所述至少一个漏极上形成第二接触区域; 去除所述至少一个牺牲栅极; 形成至少一个栅极; 以及在所述第一接触区域和所述第二接触区域上形成至少一个小接触。 还公开了一种中间半导体器件。

公开(公告)号：US09425252B1

公开(公告)日：2016-08-23

申请号：US14609653

申请日：2015-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu

IPC: H01L21/336 ,  H01L21/00 ,  H01L21/84 ,  H01L21/76 ,  H01L21/70 ,  H01L29/06 ,  H01L29/10 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/02164 ,  H01L21/28017 ,  H01L21/28238 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/1079 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a SDB including a protective layer or bilayer and the resulting device are provided. Embodiments include forming a SDB of oxide in a Si substrate; forming a nitride layer over the Si substrate; forming a photoresist over the SDB and a portion of the nitride layer; removing the nitride layer on opposite sides of the photoresist down to the Si substrate, leaving a portion of the nitride layer only under the photoresist; forming a gate above the SBD and the portion of the nitride layer.

Abstract translation: 提供了形成包括保护层或双层的SDB的方法和所得到的器件。 实施例包括在Si衬底中形成氧化物的SDB; 在Si衬底上形成氮化物层; 在所述SDB和所述氮化物层的一部分上形成光致抗蚀剂; 将光致抗蚀剂的相对侧上的氮化物层去除到Si衬底，留下一部分氮化物层仅在光致抗蚀剂下面; 在SBD上方形成栅极和氮化物层的部分。

公开(公告)号：US09412659B1

公开(公告)日：2016-08-09

申请号：US14609271

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang

IPC: H01L29/76 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L29/41725 ,  H01L21/28 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/535 ,  H01L27/088 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628

Abstract: There is set forth herein a method of fabricating a semiconductor structure, the method including forming a conductive metal layer over a source/drain region. The conductive metal layer in one aspect can prevent gouging of a source/drain region during removal of materials above a source/drain region. The conductive metal layer in one aspect can be used to pattern an air spacer for reduced parasitic capacitance. The conductive metal layer in one aspect can reduce a contact resistance between a source/drain region and a contact above a source/drain region.

Abstract translation: 这里阐述制造半导体结构的方法，该方法包括在源/漏区上形成导电金属层。 导电金属层在一个方面可以防止在去除源极/漏极区域之上的材料时源极/漏极区的气泡。 一方面的导电金属层可以用于图案化空气间隔物以降低寄生电容。 导电金属层在一个方面可以降低源极/漏极区域和源极/漏极区域之上的接触点之间的接触电阻。

公开(公告)号：US20160118458A1

公开(公告)日：2016-04-28

申请号：US14983157

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Bingwu Liu

IPC: H01L49/02 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide improved metal-insulator-metal (MIM) capacitors. In embodiments, series resistance is reduced by forming a via underneath the bottom plate of a MIM capacitor, leading to a metallization layer or intermediate metal sublayer. In embodiments, the MIM capacitor is formed with a corrugated shape to increase the plate surface area, allowing a thicker dielectric to be used, thereby mitigating leakage issues.

公开(公告)号：US09236481B1

公开(公告)日：2016-01-12

申请号：US14699543

申请日：2015-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Jin Ping Liu

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/49 ,  H01L29/06 ,  H01L29/66 ,  H01L21/027 ,  H01L21/311 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3213

CPC classification number: H01L29/7851 ,  H01L21/0337 ,  H01L21/28123 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/32139 ,  H01L29/66545 ,  H01L29/66795

Abstract: Semiconductor devices and methods for forming devices with ultraviolet curing. One method includes, for instance: obtaining a wafer; forming at least one mandrel; forming spacers adjacent to the at least one mandrel; performing an ultraviolet treatment to at least one set of spacers; and etching to form hard mask regions below at least the spacers. An intermediate semiconductor device includes, for instance: a substrate; a stop layer over the substrate; a first barrier layer over the stop layer; at least one first mandrel and at least one second mandrel on the first barrier layer; at least one first set of spacers positioned adjacent to the first mandrel; at least one second set of spacers positioned adjacent to the second mandrel; and a second barrier layer over the at least one first mandrel and the at least one first set of spacers.

Abstract translation: 用于形成紫外线固化装置的半导体装置和方法。 一种方法包括，例如：获得晶片; 形成至少一个心轴; 形成邻近所述至少一个心轴的间隔件; 对至少一组间隔件执行紫外线处理; 并蚀刻以至少形成间隔物以形成硬掩模区域。 中间半导体器件包括例如：衬底; 在衬底上的停止层; 停止层上的第一阻挡层; 至少一个第一心轴和所述第一阻挡层上的至少一个第二心轴; 位于第一心轴附近的至少一个第一组间隔件; 至少一个第二组间隔件邻近第二心轴定位; 以及在所述至少一个第一心轴和所述至少一个第一组间隔物上的第二阻挡层。

公开(公告)号：US09159633B2

公开(公告)日：2015-10-13

申请号：US14026172

申请日：2013-09-13

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Tenko Yamashita ,  Chun-Chen Yeh ,  Jin Cho ,  Hui Zang

IPC: H01L23/58 ,  H01L29/10 ,  H01L21/66 ,  H01L21/8234

CPC classification number: H01L22/14 ,  G03F7/70466 ,  H01L21/823431 ,  H01L22/10 ,  H01L22/12 ,  H01L22/34

Abstract: A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region and forming a first and second source/drain regions in the active area. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region. The method further includes determining if an overlay shift has occurred during the formation of the active area by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.

Abstract translation: 提供了一种使用多重图案化光刻工艺（MPLP）形成具有测试宏的集成电路的方法。 该方法包括形成具有第一和第二栅极区的测试宏的有源区，并在有源区中形成第一和第二源极/漏极区。 该方法还包括形成连接到第一栅极区域的第一触点，连接到第二栅极区域的第二触点，连接到第一源极/漏极区域的第三触点和连接到源极/漏极区域的第四触点。 该方法还包括通过测试第一接触，第二接触，第三接触或第四接触中的一个或多个之间的短路来确定在形成有源区域期间是否发生覆盖偏移。

公开(公告)号：US20210020644A1

公开(公告)日：2021-01-21

申请号：US16515913

申请日：2019-07-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bipul C. Paul ,  Ruilong Xie ,  Julien Frougier ,  Daniel Chanemougame ,  Hui Zang

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238

Abstract: Methods of forming a gate cut isolation for an SRAM include forming a first and second active nanostructures adjacent to each other and separated by a space; forming a sacrificial liner over at least a side of the first active nanostructure facing the space, causing a first distance between a remaining portion of the space and the first active nanostructure to be greater than a second distance between the remaining portion of the space and the second active nanostructure. A gate cut isolation is formed in the remaining portion of the space such that it is closer to the second active nanostructure than the first active nanostructure. The sacrificial liner is removed, and gates formed over the active nanostructures with the gates separated from each other by the gate cut isolation. An SRAM including the gate cut isolation and an IC structure including the SRAM are also included.