公开(公告)号：US10388652B2

公开(公告)日：2019-08-20

申请号：US15811961

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yongiun Shi ,  Lei Sun ,  Laertis Economikos ,  Ruilong Xie ,  Lars Liebmann ,  Chanro Park ,  Daniel Chanemougame ,  Min Gyu Sung ,  Hsien-Ching Lo ,  Haiting Wang

IPC: H01L27/088 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L27/02 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/027

Abstract: The disclosure provides integrated circuit (IC) structures with single diffusion break (SDB) abutting end isolation regions, and methods of forming the same. An IC structure may include: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on the plurality of fins and laterally between the plurality of gate structures; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins, the at least one SDB region extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region abutting a lateral end of the at least one SDB along a length of the plurality of gate structures, the end isolation region extending substantially in parallel with the plurality of fins.

公开(公告)号：US20190252267A1

公开(公告)日：2019-08-15

申请号：US16390232

申请日：2019-04-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Bentley ,  Puneet Harischandra Suvarna ,  Chanro Park ,  Min Gyu Sung ,  Lars Liebmann ,  Su Chen Fan ,  Brent Anderson

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L21/823821 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/0653 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/78642

Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a sidewall spacer that is formed over an endwall of the fin. The sidewall spacer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.

公开(公告)号：US20190214387A1

公开(公告)日：2019-07-11

申请号：US15868058

申请日：2018-01-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Judson R. Holt ,  George Mulfinger ,  Timothy J. McArdle ,  Thomas Merbeth ,  Ömür Aydin ,  Ruilong Xie

IPC: H01L27/092 ,  H01L27/11 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/82385 ,  H01L21/823871 ,  H01L27/1104 ,  H01L29/41775 ,  H01L29/66515

Abstract: One illustrative method disclosed herein includes, among other things, performing at least one etching process to expose at least a portion of an upper surface of a gate electrode of a first transistor device and at least a vertical portion of one side surface of the gate electrode and performing a material growth process to form a conductive gate-to-source/drain (GSD) contact structure that conductively couples the gate electrode of the first transistor device to a source/drain region of the first transistor device, wherein the conductive GSD contact structure comprises a non-single crystal material portion positioned on previously exposed portions of the gate electrode and a single crystal material portion positioned in the source/drain region.

公开(公告)号：US10340362B2

公开(公告)日：2019-07-02

申请号：US15938412

申请日：2018-03-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chun-chen Yeh

IPC: H01L29/66 ,  H01L29/78

Abstract: Structures for spacers of a field-effect transistor and methods for forming such spacers. A mask layer has a feature separated from a vertical sidewall of a first gate structure by a space of predetermined width that exposes a top surface of a semiconductor body. A spacer is formed adjacent to the vertical sidewall of the first gate structure. The spacer has a first section in the space and a second section. The first section of the spacer is located vertically between the second section of the spacer and the top surface of the semiconductor body. The first section of the spacer extends through the space to the top surface of the semiconductor body, and the first section of the spacer fully fills the space.

公开(公告)号：US10340189B2

公开(公告)日：2019-07-02

申请号：US15689565

申请日：2017-08-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Balasubramanian Pranatharthiharan ,  Junli Wang ,  Ruilong Xie

IPC: H01L29/51 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/10 ,  H01L21/84 ,  H01L27/12

Abstract: A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material.

公开(公告)号：US20190198381A1

公开(公告)日：2019-06-27

申请号：US16288780

申请日：2019-02-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Ruilong Xie

IPC: H01L21/768 ,  H01L29/66

CPC classification number: H01L21/7682 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

Abstract: Structures for air-gap spacers in a field-effect transistor and methods for forming air-gap spacers in a field-effect transistor. A gate structure is formed on a top surface of a semiconductor body. A dielectric spacer is formed adjacent to a vertical sidewall of the gate structure. A semiconductor layer is formed on the top surface of the semiconductor body. The semiconductor layer is arranged relative to the vertical sidewall of the gate structure such that a first section of the first dielectric spacer is located in a space between the semiconductor layer and the vertical sidewall of the gate structure. A second section of the dielectric spacer that is located above a top surface of the semiconductor layer is removed. An air-gap spacer is formed in a space from which the second section of the dielectric spacer is removed.

公开(公告)号：US10304833B1

公开(公告)日：2019-05-28

申请号：US15898812

申请日：2018-02-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Puneet Harischandra Suvarna ,  Bipul C. Paul ,  Ruilong Xie ,  Bartlomiej Jan Pawlak ,  Lars W. Liebmann ,  Daniel Chanemougame ,  Nicholas V. LiCausi ,  Andreas Knorr

IPC: H01L29/775 ,  H01L29/78 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L27/12

Abstract: A device includes a first nano-sheet of a first semiconductor material. First source/drain regions are positioned adjacent ends of the first nano-sheet. A first dielectric material is positioned above the first source/drain regions. A second nano-sheet of a second semiconductor material is positioned above the first nano-sheet. Second source/drain regions are positioned adjacent ends of the second nano-sheet and above the first dielectric material. A gate structure has a first portion capacitively coupled to the first nano-sheet and a second portion capacitively coupled to the second nano-sheet. A first source/drain contact contacts a first portion of the second source/drain regions in a first region where the first and second source/drain regions do not vertically overlap. The first source/drain contact has a first depth that extends below a height of an upper surface of the first source/drain regions in a second region where the first and second source/drain regions vertically overlap.

公开(公告)号：US10290549B2

公开(公告)日：2019-05-14

申请号：US15695229

申请日：2017-09-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Julien Frougier ,  Min Gyu Sung ,  Edward Joseph Nowak ,  Nigel G. Cave ,  Lars Liebmann ,  Daniel Chanemougame ,  Andreas Knorr

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L27/11

Abstract: The disclosure is directed to gate all-around integrated circuit structures, finFETs having a dielectric isolation, and methods of forming the same. The gate all-around integrated circuit structure may include a first insulator region within a substrate; a pair of remnant liner stubs disposed within the first insulator region; a second insulator region laterally adjacent to the first insulator region within the substrate; a pair of fins over the first insulator region, each fin in the pair of fins including an inner sidewall facing the inner sidewall of an adjacent fin in the pair of fins and an outer sidewall opposite the inner sidewall; and a gate structure substantially surrounding an axial portion of the pair of fins and at least partially disposed over the first and second insulator regions, wherein each remnant liner stub is substantially aligned with the inner sidewall of a respective fin of the pair of fins.

公开(公告)号：US10276689B2

公开(公告)日：2019-04-30

申请号：US15615925

申请日：2017-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yi Qi ,  Jianwei Peng ,  Hsien-Ching Lo ,  Ruilong Xie ,  Xunyuan Zhang ,  Hui Zang

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

Abstract: Disclosed are embodiments of an improved method for forming a vertical field effect transistor (VFET). In each of the embodiments of the method, a semiconductor fin is formed sufficiently thick (i.e., wide) so that the surface area of the top of the semiconductor fin is sufficiently large to facilitate epitaxial growth thereon of a semiconductor material for a second source/drain region. As a result, the second source/drain region will be sufficiently large to avoid potential contact-related defects (e.g., unlanded contacts, complete silicidation of second source/drain region during contact formation, etc.). Additionally, either before or after this second source/drain region is formed, at least the center portion of the semiconductor fin, which will include the channel region of the VFET, is thinned down to a desired critical dimension for optimal VFET performance. Also disclosed are VFET structure embodiments resulting from this method.

公开(公告)号：US10276659B2

公开(公告)日：2019-04-30

申请号：US15992431

申请日：2018-05-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chun-Chen Yeh ,  Kangguo Cheng ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: A vertical transistor device includes a vertically-oriented channel semiconductor (VOCS) structure positioned above a substrate and a first bottom spacer positioned above the substrate adjacent the VOCS structure. The first bottom spacer extends around less than an entirety of a perimeter of the VOCS structure. A gate structure is positioned around the VOCS structure. Only a portion of the gate structure is positioned vertically above the first bottom spacer so as to thereby define an air gap that is positioned under the gate structure. The air gap extends around a majority of a perimeter of the VOCS structure and a second bottom spacer positioned above the substrate. An upper portion of the second bottom spacer contacts a material formed around the VOCS structure so as to seal the air gap. The second bottom spacer has a vertical thickness that is greater than a vertical thickness of the air gap.