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    Non-volatile Memory Device And A Method Of Programming Such Device
    343.
    发明申请
    Non-volatile Memory Device And A Method Of Programming Such Device 有权
    非易失性存储器件及其编程方法

    公开(公告)号：US20150003166A1

    公开(公告)日：2015-01-01

    申请号：US14449926

    申请日：2014-08-01

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Thuan Vu

    IPC: G11C16/10 ,  G11C16/26 ,  H01L27/115

    CPC classification number: G11C16/10 ,  G11C7/00 ,  G11C7/22 ,  G11C16/26 ,  G11C16/28 ,  G11C2207/2263 ,  G11C2211/5647 ,  H01L27/11517

    Abstract: A non-volatile memory device has a charge pump for providing a programming current and an array of non-volatile memory cells. Each memory cell of the array is programmed by the programming current from the charge pump. The array of non-volatile memory cells is partitioned into a plurality of units, with each unit comprising a plurality of memory cells. An indicator memory cell is associated with each unit of non-volatile memory cells. A programming circuit programs the memory cells of each unit using the programming current, when fifty percent or less of the memory cells of each unit is to be programmed, and programs the inverse of the memory cells of each unit and the indicator memory cell associated with each unit, using the programming current, when more than fifty percent of the memory cells of each unit is to be programmed.

    Abstract translation: 非易失性存储器件具有用于提供编程电流和非易失性存储器单元阵列的电荷泵。 阵列的每个存储单元都由来自电荷泵的编程电流编程。 非易失性存储器单元的阵列被分割成多个单元，每个单元包括多个存储器单元。 指示器存储单元与每单位的非易失性存储单元相关联。 编程电路使用编程电流来对每个单元的存储器单元进行编程，当每个单元的存储单元的百分之五十或更少被编程时，编程每个单元的存储器单元的反相和与 每个单元使用编程电流时，每个单元的存储单元的百分之五十以上将被编程。

    Neural network classifier using array of three-gate non-volatile memory cells
    348.
    发明授权
    Neural network classifier using array of three-gate non-volatile memory cells 有权

    公开(公告)号：US12283314B2

    公开(公告)日：2025-04-22

    申请号：US18644840

    申请日：2024-04-24

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

    IPC: G11C11/54 ,  G06N3/045 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H10B41/30 ,  H10D30/68

    Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, fourth lines each electrically connect the drain regions in one of the memory cell columns, and a plurality of transistors each electrically connected in series with one of the fourth lines. The synapses receive a first plurality of inputs as electrical voltages on gates of the transistors, and provide a first plurality of outputs as electrical currents on the third lines.

    OUTPUT CIRCUIT FOR A VECTOR-BY-MATRIX MULTIPLICATION ARRAY
    350.
    发明申请
    OUTPUT CIRCUIT FOR A VECTOR-BY-MATRIX MULTIPLICATION ARRAY 有权

    公开(公告)号：US20250068900A1

    公开(公告)日：2025-02-27

    申请号：US18386901

    申请日：2023-11-03

    Applicant: Silicon Storage Technology, Inc.

    Inventor： HIEU VAN TRAN ,  ANDREW KUNIL CHOE ,  HOA VU

    IPC: G06N3/065

    Abstract: In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns, a first set of columns storing W+ weights and a second set of columns storing W− weights; and an output circuit to receive a first current from a respective column in the first set of columns and a second current from a respective column in the second set of columns and to generate a first voltage and a second voltage, the output circuit comprising a first current-to-voltage converter comprising a first integration capacitor to provide the first voltage equal to an initial voltage minus a first discharge value due to the first current, and a second current-to-voltage converter comprising a second integration capacitor to provide the second voltage equal to the initial voltage minus a second discharge value due to the second current.

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