公开(公告)号：US09941319B2

公开(公告)日：2018-04-10

申请号：US14936657

申请日：2015-11-09

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar

IPC: H04N5/225 ,  H04N5/232 ,  H01L27/118 ,  H01L21/70 ,  H01L27/146 ,  H01L25/075 ,  H01L33/38

CPC classification number: H01L27/14634 ,  H01L25/0756 ,  H01L27/14623 ,  H01L27/14629 ,  H01L27/14647 ,  H01L27/1469 ,  H01L33/382

Abstract: A method for processing a semiconductor wafer, the method including: providing a semiconductor wafer including an image sensor pixels layer including a plurality of image sensor pixels, the layer overlaying a wafer substrate; and then bonding the semiconductor wafer to a carrier wafer; and then cutting off a substantial portion of the wafer substrate, and then processing the substantial portion of the wafer substrate for reuse.

公开(公告)号：US09941275B2

公开(公告)日：2018-04-10

申请号：US15470872

申请日：2017-03-27

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/06 ,  H01L23/544 ,  H01L27/088 ,  H01L23/58 ,  H01L23/00 ,  H01L23/367 ,  H01L27/092

CPC classification number: H01L27/0688 ,  H01L23/3677 ,  H01L23/544 ,  H01L23/552 ,  H01L23/562 ,  H01L23/585 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1211 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: An Integrated Circuit device, including: a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single crystal transistors, where the second layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of the first transistors that cross the first dice lane, where a plurality of the second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to the plurality of the second transistors that cross the second dice lane, and at least one thermal conducting path from at least one of the second single crystal transistors to an external surface of the device.

公开(公告)号：US20180069052A1

公开(公告)日：2018-03-08

申请号：US15803732

申请日：2017-11-03

Applicant: Monolithic 3D Inc.

Inventor： Deepak C. Sekar ,  Zvi Or-Bach

IPC: H01L27/24 ,  H01L27/22

CPC classification number: H01L27/2481 ,  H01L21/268 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1203 ,  H01L27/1211 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/42392 ,  H01L29/7841 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2029/7857 ,  H01L2221/6835

Abstract: A 3D semiconductor device, the device including: first transistors; second transistors, overlaying the first transistors; third transistors, overlaying the second transistors; and fourth transistors, overlaying the third transistors, where the second transistors, the third transistors and the fourth transistors are self-aligned, being processed following the same lithography step, and where at least one of the first transistors is part of a control circuit controlling at least one of the second transistors, at least one of the third transistors and at least one of the fourth transistors.

公开(公告)号：US09786636B2

公开(公告)日：2017-10-10

申请号：US15008444

申请日：2016-01-28

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L21/00 ,  H01L25/065 ,  H01L21/768 ,  H01L23/48 ,  H01L23/485 ,  H01L23/522 ,  H01L29/66 ,  H01L21/74 ,  H01L25/00 ,  H01L27/06 ,  H01L27/088 ,  H01L23/36 ,  H01L29/423 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L25/0657 ,  H01L21/743 ,  H01L21/76898 ,  H01L23/36 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5225 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/78 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01104 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/2064 ,  H01L2924/351 ,  H01L2924/00

Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a first wire structure constructed to provide power to a portion of the first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; and a second wire structure constructed to provide power to a portion of the second transistors, where the second wire structure is isolated from the first wire structure to provide a different power voltage to the portion of the second transistors.

公开(公告)号：US20170133432A1

公开(公告)日：2017-05-11

申请号：US15409740

申请日：2017-01-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Zeev Wurman

IPC: H01L27/24 ,  H01L29/66 ,  H01L29/167 ,  H01L29/78 ,  H01L45/00 ,  H01L29/04

CPC classification number: H01L27/2436 ,  G11C13/0021 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/2236 ,  H01L21/31116 ,  H01L21/324 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/249 ,  H01L29/04 ,  H01L29/167 ,  H01L29/66568 ,  H01L29/78 ,  H01L29/78696 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1616 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/00011 ,  H01L2224/80001

Abstract: A semiconductor memory, including: a first memory cell including a first transistor; a second memory cell including a second transistor; and a memory peripherals transistor overlaying the second transistor or underneath the first transistor, where the second memory cell overlays the first memory cell, and where the first memory cell and the second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and where the memory peripherals transistor is part of a peripherals circuit controlling the memory.

公开(公告)号：US20170062600A1

公开(公告)日：2017-03-02

申请号：US15351389

申请日：2016-11-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Yuniarto Widjaja

IPC: H01L29/78 ,  H01L27/115 ,  H01L27/24 ,  H01L27/11 ,  H01L27/108

CPC classification number: H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/412 ,  G11C16/02 ,  G11C16/0483 ,  G11C2213/71 ,  H01L27/10802 ,  H01L27/1104 ,  H01L27/115 ,  H01L27/11578 ,  H01L27/2436 ,  H01L29/7841

Abstract: A 3D IC based system, the system including: a first layer including first memory cells including first transistors, where the first transistors include first transistor channels; a second layer overlying the first layer, the second layer including second memory cells including second transistors, where the second transistors include second transistor channels, where the second layer includes vertically oriented doped regions, where the second layer includes at least one through second layer via having a diameter of less than 400 nm, and where at least one of the first transistor channels and at least one of the second transistor channels are directly coupled to at least one of the vertically oriented doped region.

Abstract translation: 一种基于3D IC的系统，该系统包括：第一层，包括包括第一晶体管的第一存储单元，其中第一晶体管包括第一晶体管沟道; 覆盖第一层的第二层，第二层包括包括第二晶体管的第二存储单元，其中第二晶体管包括第二晶体管沟道，其中第二层包括垂直取向的掺杂区域，其中第二层包括至少一个至第二层通孔 具有小于400nm的直径，并且其中第一晶体管沟道和至少一个第二晶体管沟道中的至少一个直接耦合到垂直取向的掺杂区域中的至少一个。

公开(公告)号：US20160343774A1

公开(公告)日：2016-11-24

申请号：US15224929

申请日：2016-08-01

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Zeev Wurman

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/00011 ,  H01L2224/80001

Abstract: A semiconductor device, including: a first memory cell including a first transistor; a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor self-aligned to the first transistor; and a plurality of junctionless transistors, where at least one of the junctionless transistors controls access to at least one of the memory cells.

Abstract translation: 一种半导体器件，包括：包括第一晶体管的第一存储单元; 第二存储单元，包括第二晶体管，其中所述第二晶体管覆盖所述第一晶体管，所述第二晶体管与所述第一晶体管自对准; 以及多个无连接晶体管，其中至少一个无连接晶体管控制对至少一个存储单元的访问。

公开(公告)号：US09460991B1

公开(公告)日：2016-10-04

申请号：US13864242

申请日：2013-04-17

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L21/70 ,  H01L23/62 ,  H01L23/498

CPC classification number: H01L21/4871 ,  H01L21/823487 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/3732 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/60 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/098 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A 3D semiconductor device, including: a first layer including first transistors; a second layer overlying the first transistors and including second transistors; wherein the second layer includes a through layer via with a diameter of less than 150 nm; and a first circuit including at least one of the first transistors, and the first circuit has a first circuit output connected to at least one of the second transistors, wherein the at least one of the second transistors is connected to a device output that is designed to be connected to external devices, and wherein the at least one of the second transistors is substantially larger than the at least one of the first transistors.

Abstract translation: 一种3D半导体器件，包括：包括第一晶体管的第一层; 覆盖所述第一晶体管并包括第二晶体管的第二层; 其中所述第二层包括直径小于150nm的贯通层通孔; 以及第一电路，其包括所述第一晶体管中的至少一个，并且所述第一电路具有连接到所述第二晶体管中的至少一个的第一电路输出，其中所述第二晶体管中的至少一个连接到设计的器件输出 以连接到外部设备，并且其中所述第二晶体管中的至少一个基本上大于所述至少一个所述第一晶体管。

公开(公告)号：US09419031B1

公开(公告)日：2016-08-16

申请号：US14461539

申请日：2014-08-18

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak Sekar

IPC: H01L27/146 ,  H01L21/822

CPC classification number: H01L27/14605 ,  H01L21/8221 ,  H01L25/0756 ,  H01L27/14612 ,  H01L27/14634 ,  H01L27/153 ,  H01L31/0725 ,  H01L31/1892 ,  H01L33/0079 ,  H01L33/34 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/00

Abstract: An integrated device, including: a first mono-crystal layer including a plurality of image sensor pixels and alignment marks; an overlaying oxide on top of the first mono-crystal layer; and a second mono-crystal layer overlaying the oxide, where the second mono-crystal layer includes a plurality of single crystal transistors aligned to the alignment marks.

Abstract translation: 一种集成装置，包括：包括多个图像传感器像素和对准标记的第一单晶层; 在第一单晶层的顶部上的覆盖氧化物; 以及覆盖所述氧化物的第二单晶层，其中所述第二单晶层包括与所述对准标记对准的多个单晶体晶体管。

公开(公告)号：US09385088B2

公开(公告)日：2016-07-05

申请号：US14626563

申请日：2015-02-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L23/538 ,  H01L45/00 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11 ,  H01L27/06 ,  H01L27/088 ,  H01L27/085 ,  H01L27/092 ,  H01L27/22 ,  H01L27/24

CPC classification number: H01L23/5386 ,  H01L27/0688 ,  H01L27/085 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/1108 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1675 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor device including: a first layer including first transistors including at least one first monocrystalline silicon transistor channel; a second layer including second transistors including at least one second monocrystalline non-silicon transistor channel; a plurality of connection paths extending from the second transistors to the first transistors, where at least one of the connection paths includes at least one through layer via with a diameter of less than 200 nm.

Abstract translation: 一种半导体器件，包括：包括第一晶体管的第一层，所述第一晶体管包括至少一个第一单晶硅晶体管沟道; 第二层，包括包括至少一个第二单晶非硅晶体管沟道的第二晶体管; 从第二晶体管延伸到第一晶体管的多个连接路径，其中至少一个连接路径包括直径小于200nm的至少一个贯穿层通孔。