公开(公告)号：US20150235929A1

公开(公告)日：2015-08-20

申请号：US14615673

申请日：2015-02-06

Applicant: STMicroelectronics (Malta) Ltd ,  STMicroelectronics S.r.I. ,  STMicroelectronics Pte Ltd

Inventor： Roseanne Duca ,  Valter Motta ,  Xueren Zhang ,  Kim-Yong Goh

IPC: H01L23/495

CPC classification number: H01L23/49568 ,  H01L23/4334 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2924/18301 ,  H01L2924/00014

Abstract: An electronic device includes an integrated circuit chip mounted to a heat slug. The heat slug has a peripheral region having first thickness along a first direction, the peripheral region surrounding a recess region (having a second, smaller, thickness along the first direction) that defines a chip mounting surface along a second direction perpendicular to the first direction. The recess region defines side borders and a nook extends into the heat slug along the side borders. An insulating body embeds the integrated circuit one chip and heat slug. Material of the insulating body fills the nook.

Abstract translation: 一种电子设备包括安装在散热片上的集成电路芯片。 散热片具有沿着第一方向具有第一厚度的周边区域，周边区域围绕沿着垂直于第一方向的第二方向限定芯片安装表面的凹陷区域（具有沿着第一方向的第二较小厚度） 。 凹槽区域限定侧面边界，并且角部沿着侧边缘延伸到热塞中。 绝缘体嵌入集成电路一芯片和散热片。 绝缘体的材料填充角。

公开(公告)号：US09011776B2

公开(公告)日：2015-04-21

申请号：US14013730

申请日：2013-08-29

Applicant: STMicroelectronics S.r.I.

Inventor： Federico Giovanni Ziglioli ,  Fulvio Vittorio Fontana ,  Luca Maggi

IPC: B81C1/00 ,  B81B7/00 ,  H04R19/04

CPC classification number: B81B7/0077 ,  B81B7/0058 ,  B81B2201/0264 ,  B81C1/00333 ,  B81C2203/0118 ,  H01L2224/48091 ,  H01L2224/48145 ,  H04R1/086 ,  H04R19/04 ,  H04R2201/003 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A packaged device, wherein at least one sensitive portion of a chip is enclosed in a chamber formed by a package. The package has an air-permeable area having a plurality of holes and a liquid-repellent structure so as to enable passage of air between an external environment and the chamber and block the passage of liquids.

Abstract translation: 一种封装器件，其中芯片的至少一个敏感部分被封装在由封装形成的腔室中。 该包装具有透气区域，具有多个孔和拒水结构，以使得能够在外部环境和室之间通过空气并阻止液体的通过。

公开(公告)号：US08996943B2

公开(公告)日：2015-03-31

申请号：US13722594

申请日：2012-12-20

Applicant: STMicroelectronics Pvt. Ltd. ,  STMicroelectronics S.r.I.

Inventor： Nicolas Bernard Grossier ,  Sabyasachi Das ,  V Srinivasan

IPC: G06F11/00 ,  G05F1/56 ,  G01R31/00 ,  G01R31/319 ,  G05F1/10

CPC classification number: G05F1/56 ,  G01R31/00 ,  G01R31/31924 ,  G05F1/10

Abstract: A Voltage regulator includes a first input terminal configured to receive an input supply voltage, includes a second input terminal configured to receive a regulated output supply voltage as a function of the input supply voltage or to receive a test supply voltage and comprises a power transistor including an input terminal configured to receive the input supply voltage and including an output terminal configured to generate the regulated output supply voltage. The Voltage regulator is configured, during a start-up phase of a test operation mode, to receive a control signal equal to the input supply voltage, is configured to receive the input supply voltage having a substantially increasing trend, detect that the input supply voltage is equal to a first voltage threshold and generate, as a function of the detected signal and of the control signal, a by-pass signal having a transition from a first logic value to a second logic value for indicating a by-pass status of the Voltage regulator, and is configured to receive the by-pass signal having the second logic value and open the power transistor. The second input terminal is configured, during the test operation mode, to receive the test supply voltage having a test value different from a nominal value of the regulated output supply voltage.

Abstract translation: 电压调节器包括被配置为接收输入电源电压的第一输入端子，包括被配置为接收作为输入电源电压的函数的调节输出电源电压或者接收测试电源电压的第二输入端子，并且包括功率晶体管，包括 输入端子，被配置为接收所述输入电源电压并且包括被配置为产生所述稳定的输出电源电压的输出端子。 电压调节器在测试操作模式的启动阶段被配置为接收等于输入电源电压的控制信号，被配置为接收具有基本上增加的趋势的输入电源电压，检测输入电源电压 等于第一电压阈值，并且根据所检测的信号和控制信号产生具有从第一逻辑值到第二逻辑值的转变的旁路信号，用于指示所述第一电压阈值的旁路状态 电压调节器，并且被配置为接收具有第二逻辑值的旁路信号并且打开功率晶体管。 在测试操作模式期间，第二输入端被配置为接收具有与调节输出电源电压的标称值不同的测试值的测试电源电压。

公开(公告)号：US20150054538A1

公开(公告)日：2015-02-26

申请号：US14533526

申请日：2014-11-05

Applicant: STMicroelectronics S.r.I.

Inventor： Alberto Pagani

IPC: G01R1/18 ,  G01R31/28 ,  G01R1/073

CPC classification number: G01R1/18 ,  G01R1/06772 ,  G01R1/07307 ,  G01R31/2884 ,  G01R31/2886

Abstract: A probe card includes a number probes. Each probe is adapted to contact a corresponding terminal of a circuit integrated in at least one die of a semiconductor material wafer during a test phase of the wafer. The probes include at least one probe adapted to provide and/or receive a radio frequency test signal to/from the corresponding terminal during the test phase. The probe card further includes at least one electromagnetic shield structure corresponding to the at least one probe adapted to provide and/or receive the radio frequency test signal for the at least partial shielding of an electromagnetic field irradiated by such at least one probe adapted to provide and/or receive the radio frequency test signal.

Abstract translation: 探针卡包括数字探针。 每个探针适于在晶片的测试阶段期间接触集成在半导体材料晶片的至少一个管芯中的电路的相应端子。 探针包括适于在测试阶段期间向/从相应终端提供和/或接收射频测试信号的至少一个探头。 探针卡还包括对应于至少一个探头的至少一个电磁屏蔽结构，适于提供和/或接收射频测试信号，用于至少部分屏蔽由这样的至少一个探头照射的电磁场，该探针适于提供 和/或接收射频测试信号。

公开(公告)号：US20140312878A1

公开(公告)日：2014-10-23

申请号：US14322448

申请日：2014-07-02

Applicant: STMICROELECTRONICS S.r.I.

Inventor： Daniele Alfredo BRAMBILLA ,  Fausto REDIGOLO

IPC: H01L21/66 ,  G01R19/00 ,  H01L49/02

CPC classification number: H01L22/20 ,  G01R19/0092 ,  H01L22/12 ,  H01L23/544 ,  H01L28/20 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2223/5448 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Indexing a plurality of die obtainable from a material wafer comprising a plurality of stacked material layers. Each die is obtained in a respective position of the wafer. A manufacturing stage comprises at least two steps for treating a respective superficial portion of the material wafer that corresponds to a subset of said plurality of dies using the at least one lithographic mask through the exposition to the proper radiation in temporal succession. The method may include providing a die index on each die which is indicative of the position of the respective die by forming an external index indicative of the position of the superficial portion of the material wafer corresponding to the subset of the plurality of dies including said die and may comprise a plurality of electronic components electrically coupled to each other by means of a respective common control line.

Abstract translation: 对从包括多个堆叠的材料层的材料晶片获得的多个管芯进行索引。 在晶片的相应位置获得每个管芯。 制造阶段包括至少两个步骤，用于使用至少一个光刻掩模通过在时间上连续地暴露于合适的辐射来处理对应于所述多个管芯的子集的材料晶片的相应表面部分。 该方法可以包括通过形成指示材料晶片的表面部分的位置的外部指标来指示相应管芯的位置来指示每个管芯上的管芯指数，该外部指数对应于包括所述管芯的多个管芯的子集 并且可以包括通过相应的公共控制线彼此电耦合的多个电子部件。

公开(公告)号：US20140300005A1

公开(公告)日：2014-10-09

申请号：US14304111

申请日：2014-06-13

Applicant: STMicroelectronics S.r.I.

Inventor： Antonio Di Franco ,  Marco Bonifacio ,  Silvio Cristofalo

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76877 ,  H01L21/02274 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76819 ,  H01L21/76837 ,  H01L23/481 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multilevel interconnect structure for a semiconductor device includes an intermetal dielectric layer with funnel-shaped connecting vias. The funnel-shaped connecting vias are provided in connection with systems exhibiting submicron spacings. The architecture of the multilevel interconnect structure provides a low resistance connecting via.

公开(公告)号：US20140292419A1

公开(公告)日：2014-10-02

申请号：US14216037

申请日：2014-03-17

Applicant: STMicroelectronics S.r.I.

Inventor： Egidio Ragonese ,  Vincenzo Fiore ,  Nunzio Spina ,  Giuseppe Palmisano

IPC: H03B5/02

CPC classification number: H03B5/1212 ,  H03B1/02 ,  H03B5/02 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1296 ,  H03B27/00 ,  H03B2200/0074 ,  H03B2200/0076 ,  H03B2200/0078

Abstract: An oscillator circuit includes first and second oscillators arranged in a series configuration between a supply voltage node and a reference voltage node. The first and second oscillators are configured to receive a synchronizing signal for controlling synchronization in frequency and phase. An electromagnetic network provided to couple the first and the second oscillators includes a transformer with a primary circuit and a secondary circuit. The primary circuit includes a first portion coupled to the first oscillator and second portion coupled to the second oscillator. The first and second portions are connected by a circuit element for reuse of current between the first and second oscillators. The oscillator circuit is fabricated as an integrated circuit device wherein the electromagnetic network is formed in metallization layers of the device. The secondary circuit generates an output power combining power provided from the first and second portions of the primary circuit.

Abstract translation: 振荡器电路包括在电源电压节点和参考电压节点之间以串联配置布置的第一和第二振荡器。 第一和第二振荡器被配置为接收用于控制频率和相位同步的同步信号。 提供用于耦合第一和第二振荡器的电磁网络包括具有初级电路和次级电路的变压器。 主电路包括耦合到第一振荡器的第一部分和耦合到第二振荡器的第二部分。 第一和第二部分由用于在第一和第二振荡器之间重新使用电流的电路元件连接。 振荡器电路被制造为集成电路器件，其中电磁网络形成在器件的金属化层中。 次级电路产生从主电路的第一和第二部分提供的输出功率组合功率。

公开(公告)号：US20140291850A1

公开(公告)日：2014-10-02

申请号：US14228370

申请日：2014-03-28

Applicant: STMicroelectronics S.r.I.

Inventor： Federico Giovanni ZIGLIOLI

IPC: H01L23/00

CPC classification number: H01L24/45 ,  B81C1/0023 ,  G01L9/0044 ,  G01L19/0076 ,  H01L21/561 ,  H01L23/3114 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05611 ,  H01L2224/16145 ,  H01L2224/2405 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/45014 ,  H01L2224/45032 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48145 ,  H01L2224/48611 ,  H01L2224/48711 ,  H01L2224/48811 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/8293 ,  H01L2224/85205 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/43 ,  H01L2924/01029

Abstract: An embodiment for manufacturing electronic devices is proposed. The embodiment includes the following phases: a) forming a plurality of chips in a semiconductor material wafer including a main surface; each chip includes respective integrated electronic components and respective contact pads facing the main surface; said contact pads are electrically coupled to the integrated electronic components; b) attaching at least one conductive ribbon to at least one contact pad of each chip; c) covering the main surface of the semiconductor material wafer and the at least one conductive ribbon with a layer of plastic material; d) lapping an exposed surface of the layer of plastic material to remove a portion of the plastic material layer at least to uncover portions of the at least one conductive ribbon, and e) sectioning the semiconductor material wafer to separate the chips.

Abstract translation: 提出了制造电子装置的实施例。 该实施例包括以下阶段：a）在包括主表面的半导体材料晶片中形成多个芯片; 每个芯片包括面向主表面的相应的集成电子部件和相应的接触垫片; 所述接触垫电耦合到集成电子部件; b）将至少一个导电带附接到每个芯片的至少一个接触垫; c）用一层塑料材料覆盖半导体材料晶片的主表面和至少一个导电带; d）研磨塑料材料层的暴露表面以去除塑料材料层的一部分，以至少露出至少一个导电带的部分，以及e）切割半导体材料晶片以分离芯片。

公开(公告)号：US20140289439A1

公开(公告)日：2014-09-25

申请号：US14219850

申请日：2014-03-19

Applicant: STMicroelectronics S.r.I ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Daniele Mangano ,  Ignazio Antonino Urzi

IPC: G06F13/40

CPC classification number: G06F13/4027 ,  G06F13/14 ,  G06F15/7825 ,  G06F2213/0038 ,  H04Q2213/13399 ,  H04Q2213/399

Abstract: A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another.

Abstract translation: 诸如片上系统的系统包括通过IP块生成交易的接口组件或PLUG，诸如通过虚拟通道服务于一个或多个客户端的互连。 客户端或客户端通过客户端/虚拟通道映射映射到虚拟通道。 虚拟通道被提供为与IP块中的第二组虚拟通道协作的接口组件中的第一组虚拟通道。 提供了第一组虚拟通道和第二组虚拟通道的第一和第二客户端/虚拟通道映射。 第一个和第二个客户端/虚拟通道映射是单独可编程的，并且彼此相互解耦。

公开(公告)号：US20140247517A1

公开(公告)日：2014-09-04

申请号：US13781908

申请日：2013-03-01

Applicant: STMICROELECTRONICS S.R.I. ,  STMICROELECTRONICS ASIA PACIFIC PTE. LTD.

Inventor： Frederic Bonvin ,  Davide Betta ,  Seng-Chean Hong

IPC: G11B33/12

CPC classification number: G11B19/047 ,  G06F1/30 ,  G11B19/2072 ,  G11B19/2081

Abstract: Applicant has recognized and appreciated the desirability of powering an actuator using power drawn from one or both of an energy storage device and a spindle motor. In some embodiments, following a loss of external power to a hard disk drive, the hard disk drive (or one or more components thereof) determines whether to provide the actuator with power drawn from the spindle motor or to provide the actuator with power drawn from the spindle motor and from the energy storage device. In some embodiments, the hard disk drive (or the component(s) thereof) may additionally or alternatively determine whether to charge the energy storage device using power drawn from the spindle motor. In some embodiments, the drive may make the determinations based on an amount of power that the actuator is to consume at a time and an amount of power that the spindle motor can provide at the time.

Abstract translation: 申请人已经认识到并且认识到使用从能量存储装置和主轴电动机中的一个或两个引出的功率来驱动致动器的可取性。 在一些实施例中，在硬盘驱动器的外部电力损失之后，硬盘驱动器（或其一个或多个部件）确定是否向主动器提供从主轴电动机提取的功率，或向致动器提供从 主轴电机和储能装置。 在一些实施例中，硬盘驱动器（或其组件）可另外或替代地确定是否使用从主轴电动机抽取的功率对能量存储装置进行充电。 在一些实施例中，驱动器可以基于执行器一次消耗的功率量和主轴电机在此时可提供的功率量来进行确定。